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instead of requiring all "short description" strings to begin with two spaces. This makes these strings less mysterious, and it fixes some cases where short description strings mistakenly did not begin with two spaces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57521 91177308-0d34-0410-b5e6-96231b3b80d8
189 lines
6.2 KiB
C++
189 lines
6.2 KiB
C++
//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Top-level implementation for the PowerPC target.
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//
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//===----------------------------------------------------------------------===//
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#include "PPC.h"
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#include "PPCTargetAsmInfo.h"
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#include "PPCTargetMachine.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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// Register the targets
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static RegisterTarget<PPC32TargetMachine>
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X("ppc32", "PowerPC 32");
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static RegisterTarget<PPC64TargetMachine>
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Y("ppc64", "PowerPC 64");
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// No assembler printer by default
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PPCTargetMachine::AsmPrinterCtorFn PPCTargetMachine::AsmPrinterCtor = 0;
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const TargetAsmInfo *PPCTargetMachine::createTargetAsmInfo() const {
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if (Subtarget.isDarwin())
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return new PPCDarwinTargetAsmInfo(*this);
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else
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return new PPCLinuxTargetAsmInfo(*this);
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}
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unsigned PPC32TargetMachine::getJITMatchQuality() {
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#if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER) || defined(__PPC__)
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if (sizeof(void*) == 4)
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return 10;
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#endif
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return 0;
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}
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unsigned PPC64TargetMachine::getJITMatchQuality() {
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#if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER) || defined(__PPC__)
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if (sizeof(void*) == 8)
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return 10;
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#endif
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return 0;
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}
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unsigned PPC32TargetMachine::getModuleMatchQuality(const Module &M) {
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// We strongly match "powerpc-*".
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std::string TT = M.getTargetTriple();
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if (TT.size() >= 8 && std::string(TT.begin(), TT.begin()+8) == "powerpc-")
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return 20;
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// If the target triple is something non-powerpc, we don't match.
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if (!TT.empty()) return 0;
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if (M.getEndianness() == Module::BigEndian &&
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M.getPointerSize() == Module::Pointer32)
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return 10; // Weak match
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else if (M.getEndianness() != Module::AnyEndianness ||
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M.getPointerSize() != Module::AnyPointerSize)
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return 0; // Match for some other target
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return getJITMatchQuality()/2;
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}
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unsigned PPC64TargetMachine::getModuleMatchQuality(const Module &M) {
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// We strongly match "powerpc64-*".
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std::string TT = M.getTargetTriple();
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if (TT.size() >= 10 && std::string(TT.begin(), TT.begin()+10) == "powerpc64-")
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return 20;
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if (M.getEndianness() == Module::BigEndian &&
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M.getPointerSize() == Module::Pointer64)
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return 10; // Weak match
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else if (M.getEndianness() != Module::AnyEndianness ||
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M.getPointerSize() != Module::AnyPointerSize)
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return 0; // Match for some other target
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return getJITMatchQuality()/2;
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}
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PPCTargetMachine::PPCTargetMachine(const Module &M, const std::string &FS,
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bool is64Bit)
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: Subtarget(*this, M, FS, is64Bit),
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DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
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FrameInfo(*this, is64Bit), JITInfo(*this, is64Bit), TLInfo(*this),
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InstrItins(Subtarget.getInstrItineraryData()), MachOWriterInfo(*this) {
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if (getRelocationModel() == Reloc::Default) {
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if (Subtarget.isDarwin())
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setRelocationModel(Reloc::DynamicNoPIC);
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else
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setRelocationModel(Reloc::Static);
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}
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}
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/// Override this for PowerPC. Tail merging happily breaks up instruction issue
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/// groups, which typically degrades performance.
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bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
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PPC32TargetMachine::PPC32TargetMachine(const Module &M, const std::string &FS)
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: PPCTargetMachine(M, FS, false) {
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}
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PPC64TargetMachine::PPC64TargetMachine(const Module &M, const std::string &FS)
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: PPCTargetMachine(M, FS, true) {
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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bool PPCTargetMachine::addInstSelector(PassManagerBase &PM, bool Fast) {
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// Install an instruction selector.
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PM.add(createPPCISelDag(*this));
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return false;
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}
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bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM, bool Fast) {
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// Must run branch selection immediately preceding the asm printer.
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PM.add(createPPCBranchSelectionPass());
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return false;
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}
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bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM, bool Fast,
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raw_ostream &Out) {
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assert(AsmPrinterCtor && "AsmPrinter was not linked in");
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if (AsmPrinterCtor)
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PM.add(AsmPrinterCtor(Out, *this));
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return false;
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}
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bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM, bool Fast,
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bool DumpAsm, MachineCodeEmitter &MCE) {
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// The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
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// FIXME: This should be moved to TargetJITInfo!!
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if (Subtarget.isPPC64()) {
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// We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
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// instructions to materialize arbitrary global variable + function +
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// constant pool addresses.
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setRelocationModel(Reloc::PIC_);
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// Temporary workaround for the inability of PPC64 JIT to handle jump
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// tables.
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DisableJumpTables = true;
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} else {
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setRelocationModel(Reloc::Static);
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}
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// Inform the subtarget that we are in JIT mode. FIXME: does this break macho
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// writing?
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Subtarget.SetJITMode();
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// Machine code emitter pass for PowerPC.
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PM.add(createPPCCodeEmitterPass(*this, MCE));
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if (DumpAsm) {
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assert(AsmPrinterCtor && "AsmPrinter was not linked in");
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if (AsmPrinterCtor)
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PM.add(AsmPrinterCtor(errs(), *this));
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}
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return false;
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}
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bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM, bool Fast,
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bool DumpAsm, MachineCodeEmitter &MCE) {
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// Machine code emitter pass for PowerPC.
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PM.add(createPPCCodeEmitterPass(*this, MCE));
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if (DumpAsm) {
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assert(AsmPrinterCtor && "AsmPrinter was not linked in");
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if (AsmPrinterCtor)
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PM.add(AsmPrinterCtor(errs(), *this));
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}
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return false;
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}
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