llvm-6502/lib/CodeGen/SelectionDAG
Bob Wilson 67ba22318b Fix a minor bug in DAGCombiner's folding of SELECT. Folding "select C, 0, 1"
to "C ^ 1" is only valid when C is known to be either 0 or 1.  Most of the
similar foldings in this function only handle "i1" types, but this one appears
intentionally written to handle larger integer types.  If C has an integer
type larger than "i1", this needs to check if the high bits of a boolean
are known to be zero.  I also changed the comment to describe this folding as
"C ^ 1" instead of "~C", since that is what the code does and since the latter
would only be valid for "i1" types.  The good news is that most LLVM targets
use TargetLowering::ZeroOrOneBooleanContent so this change will not disable
the optimization; the bad news is that I've been unable to come up with a
testcase to demonstrate the problem.

I have also removed a "FIXME" comment for folding "select C, X, 0" to "C & X",
since the code looks correct to me.  It could be made more aggressive by not
limiting the type to "i1", but that would then require checking for
TargetLowering::ZeroOrNegativeOneBooleanContent.  Similar changes could be
done for the other SELECT foldings, but it was decided to be not worth the
trouble and complexity (see e.g., r44663).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62790 91177308-0d34-0410-b5e6-96231b3b80d8
2009-01-22 22:05:48 +00:00
..
CallingConvLower.cpp Add "inreg" field to CallSDNode (doesn't increase 2008-09-26 19:31:26 +00:00
CMakeLists.txt Experimental post-pass scheduling support. Post-pass scheduling 2008-11-19 23:18:57 +00:00
DAGCombiner.cpp Fix a minor bug in DAGCombiner's folding of SELECT. Folding "select C, 0, 1" 2009-01-22 22:05:48 +00:00
FastISel.cpp Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead. 2009-01-22 09:10:11 +00:00
LegalizeDAG.cpp Add SelectionDAG::getNOT method to construct bitwise NOT operations, 2009-01-22 17:39:32 +00:00
LegalizeFloatTypes.cpp Cleanup whitespace and comments, and tweak some 2009-01-21 09:00:29 +00:00
LegalizeIntegerTypes.cpp Cleanup whitespace and comments, and tweak some 2009-01-21 09:00:29 +00:00
LegalizeTypes.cpp Cleanup whitespace and comments, and tweak some 2009-01-21 09:00:29 +00:00
LegalizeTypes.h Cleanup whitespace and comments, and tweak some 2009-01-21 09:00:29 +00:00
LegalizeTypesGeneric.cpp Preserve SourceValue information when lowering produces multiple loads from 2008-12-16 18:25:36 +00:00
LegalizeVectorTypes.cpp Added missing support to widen an operand from a bit convert. 2009-01-15 22:43:38 +00:00
Makefile Removed trailing whitespace from Makefiles. 2009-01-09 16:44:42 +00:00
ScheduleDAGFast.cpp Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph 2009-01-15 19:20:50 +00:00
ScheduleDAGList.cpp Initial hazard recognizer support in post-pass scheduling. This includes 2009-01-16 01:33:36 +00:00
ScheduleDAGRRList.cpp Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph 2009-01-15 19:20:50 +00:00
ScheduleDAGSDNodes.cpp CreateVirtualRegisters does trivial copy coalescing. If a node def is used by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions. 2009-01-16 20:57:18 +00:00
ScheduleDAGSDNodesEmit.cpp Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead. 2009-01-22 09:10:11 +00:00
SelectionDAG.cpp Don't create ISD::FNEG nodes after legalize if they aren't legal. 2009-01-22 21:58:43 +00:00
SelectionDAGBuild.cpp Cleanup whitespace and comments, and tweak some 2009-01-21 09:00:29 +00:00
SelectionDAGBuild.h Initial checkin of APInt'ififcation of switch lowering 2008-12-23 22:25:27 +00:00
SelectionDAGISel.cpp Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. 2009-01-20 19:12:24 +00:00
SelectionDAGPrinter.cpp Use DebugInfo interface to lower dbg_* intrinsics. 2009-01-13 00:35:13 +00:00
TargetLowering.cpp Add SelectionDAG::getNOT method to construct bitwise NOT operations, 2009-01-22 17:39:32 +00:00