llvm-6502/test/CodeGen
Andrew Trick 8dd26253f5 RegAlloc superpass: includes phi elimination, coalescing, and scheduling.
Creates a configurable regalloc pipeline.

Ensure specific llc options do what they say and nothing more: -reglloc=... has no effect other than selecting the allocator pass itself. This patch introduces a new umbrella flag, "-optimize-regalloc", to enable/disable the optimizing regalloc "superpass". This allows for example testing coalscing and scheduling under -O0 or vice-versa.

When a CodeGen pass requires the MachineFunction to have a particular property, we need to explicitly define that property so it can be directly queried rather than naming a specific Pass. For example, to check for SSA, use MRI->isSSA, not addRequired<PHIElimination>.

CodeGen transformation passes are never "required" as an analysis

ProcessImplicitDefs does not require LiveVariables.

We have a plan to massively simplify some of the early passes within the regalloc superpass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150226 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-10 04:10:36 +00:00
..
ARM RegAlloc superpass: includes phi elimination, coalescing, and scheduling. 2012-02-10 04:10:36 +00:00
CBackend Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic. 2011-11-27 06:54:59 +00:00
CellSPU Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 2012-01-17 21:44:01 +00:00
CPP Testcase for commit 149833 (use of an uninitialized variable noticed 2012-02-05 19:27:57 +00:00
Generic Move test/CodeGen/Generic/2012-02-01-CoalescerBug.ll to CodeGen/ARM, for now. It requires TARGETS=arm. 2012-02-02 11:44:58 +00:00
Hexagon VLIW specific scheduler framework that utilizes deterministic finite automaton (DFA). 2012-02-01 22:13:57 +00:00
MBlaze
Mips Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which is 2012-02-03 04:33:00 +00:00
MSP430 Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic. 2011-11-27 06:54:59 +00:00
PowerPC AggressiveAntiDepBreaker needs to skip debug values because a debug value does not have a corresponding SUnit 2012-01-16 22:53:41 +00:00
PTX PTX: Continue to fix up the register mess. 2011-12-06 17:39:48 +00:00
SPARC Sparc CodeGen: Fix AnalyzeBranch for PR 10282. Removing addSuccessor() since 2011-12-03 21:24:48 +00:00
Thumb Fix more places which should be checking for iOS, not darwin. 2012-01-04 01:55:04 +00:00
Thumb2 After r147827 and r147902, it's now possible for unallocatable registers to be 2012-01-14 01:53:46 +00:00
X86 RegAlloc superpass: includes phi elimination, coalescing, and scheduling. 2012-02-10 04:10:36 +00:00
XCore FileCheck hygiene. 2012-01-05 00:43:34 +00:00