mirror of
https://github.com/c64scene-ar/llvm-6502.git
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327be6483d
Summary:
- Conditional moves acting on 64-bit GPR's should require MIPS-IV rather than MIPS64
- ISD::MUL, and ISD::MULH[US] should be lowered on all 64-bit ISA's
Patch by David Chisnall
His work was sponsored by: DARPA, AFRL
I've added additional testcases to cover as much of the codegen changes
affecting MIPS-IV as I can. Where I've been unable to find an existing
MIPS64 testcase that can be re-used for MIPS-IV (mainly tests covering
ISD::GlobalAddress and similar), I at least agree that MIPS-IV should
behave like MIPS64. Further testcases that are fixed by this patch will follow
in my next commit. The testcases from that commit that fail for MIPS-IV without
this patch are:
LLVM :: CodeGen/Mips/2010-07-20-Switch.ll
LLVM :: CodeGen/Mips/cmov.ll
LLVM :: CodeGen/Mips/eh-dwarf-cfa.ll
LLVM :: CodeGen/Mips/largeimmprinting.ll
LLVM :: CodeGen/Mips/longbranch.ll
LLVM :: CodeGen/Mips/mips64-f128.ll
LLVM :: CodeGen/Mips/mips64directive.ll
LLVM :: CodeGen/Mips/mips64ext.ll
LLVM :: CodeGen/Mips/mips64fpldst.ll
LLVM :: CodeGen/Mips/mips64intldst.ll
LLVM :: CodeGen/Mips/mips64load-store-left-right.ll
LLVM :: CodeGen/Mips/sint-fp-store_pattern.ll
Reviewers: dsanders
Reviewed By: dsanders
CC: matheusalmeida
Differential Revision: http://reviews.llvm.org/D3343
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206183 91177308-0d34-0410-b5e6-96231b3b80d8
170 lines
3.5 KiB
LLVM
170 lines
3.5 KiB
LLVM
; RUN: llc -march=mips64el -mcpu=mips4 -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=MIPS4 %s
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; RUN: llc -march=mips64el -mcpu=mips64 -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK -check-prefix=MIPS64 %s
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@gll0 = common global i64 0, align 8
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@gll1 = common global i64 0, align 8
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define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: daddu
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%add = add nsw i64 %a1, %a0
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ret i64 %add
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}
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define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: dsubu
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%sub = sub nsw i64 %a0, %a1
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ret i64 %sub
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}
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define i64 @f4(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: and
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%and = and i64 %a1, %a0
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ret i64 %and
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}
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define i64 @f5(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: or
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%or = or i64 %a1, %a0
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ret i64 %or
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}
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define i64 @f6(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: xor
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%xor = xor i64 %a1, %a0
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ret i64 %xor
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}
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define i64 @f7(i64 %a0) nounwind readnone {
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entry:
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; CHECK: daddiu ${{[0-9]+}}, ${{[0-9]+}}, 20
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%add = add nsw i64 %a0, 20
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ret i64 %add
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}
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define i64 @f8(i64 %a0) nounwind readnone {
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entry:
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; CHECK: daddiu ${{[0-9]+}}, ${{[0-9]+}}, -20
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%sub = add nsw i64 %a0, -20
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ret i64 %sub
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}
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define i64 @f9(i64 %a0) nounwind readnone {
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entry:
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; CHECK: andi ${{[0-9]+}}, ${{[0-9]+}}, 20
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%and = and i64 %a0, 20
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ret i64 %and
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}
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define i64 @f10(i64 %a0) nounwind readnone {
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entry:
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; CHECK: ori ${{[0-9]+}}, ${{[0-9]+}}, 20
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%or = or i64 %a0, 20
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ret i64 %or
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}
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define i64 @f11(i64 %a0) nounwind readnone {
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entry:
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; CHECK: xori ${{[0-9]+}}, ${{[0-9]+}}, 20
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%xor = xor i64 %a0, 20
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ret i64 %xor
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}
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define i64 @f12(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK: mult
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%mul = mul nsw i64 %b, %a
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ret i64 %mul
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}
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define i64 @f13(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK: mult
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%mul = mul i64 %b, %a
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ret i64 %mul
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}
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define i64 @f14(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK-LABEL: f14:
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; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
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; CHECK: teq $[[R0]], $zero, 7
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; CHECK: mflo
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%0 = load i64* @gll0, align 8
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%1 = load i64* @gll1, align 8
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%div = sdiv i64 %0, %1
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ret i64 %div
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}
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define i64 @f15() nounwind readnone {
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entry:
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; CHECK-LABEL: f15:
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; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
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; CHECK: teq $[[R0]], $zero, 7
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; CHECK: mflo
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%0 = load i64* @gll0, align 8
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%1 = load i64* @gll1, align 8
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%div = udiv i64 %0, %1
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ret i64 %div
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}
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define i64 @f16(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK-LABEL: f16:
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; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
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; CHECK: teq $[[R0]], $zero, 7
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; CHECK: mfhi
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%rem = srem i64 %a, %b
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ret i64 %rem
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}
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define i64 @f17(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK-LABEL: f17:
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; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
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; CHECK: teq $[[R0]], $zero, 7
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; CHECK: mfhi
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%rem = urem i64 %a, %b
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ret i64 %rem
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}
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declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone
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define i64 @f18(i64 %X) nounwind readnone {
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entry:
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; CHECK-LABEL: f18:
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; The MIPS4 version is too long to reasonably test. At least check we don't get dclz
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; MIPS4-NOT: dclz
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; MIPS64: dclz $2, $4
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%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %X, i1 true)
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ret i64 %tmp1
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}
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define i64 @f19(i64 %X) nounwind readnone {
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entry:
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; CHECK-LABEL: f19:
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; The MIPS4 version is too long to reasonably test. At least check we don't get dclo
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; MIPS4-NOT: dclo
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; MIPS64: dclo $2, $4
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%neg = xor i64 %X, -1
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%tmp1 = tail call i64 @llvm.ctlz.i64(i64 %neg, i1 true)
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ret i64 %tmp1
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}
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define i64 @f20(i64 %a, i64 %b) nounwind readnone {
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entry:
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; CHECK-LABEL: f20:
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; CHECK: nor
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%or = or i64 %b, %a
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%neg = xor i64 %or, -1
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ret i64 %neg
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}
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