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https://github.com/c64scene-ar/llvm-6502.git
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a0a0b40aa3
(The change was landed in r230280 and caused the regression PR22674.
This version contains a fix and a test-case for PR22674).
When emitting the increment operation, SCEVExpander marks the
operation as nuw or nsw based on the flags on the preincrement SCEV.
This is incorrect because, for instance, it is possible that {-6,+,1}
is <nuw> while {-6,+,1}+1 = {-5,+,1} is not.
This change teaches SCEV to mark the increment as nuw/nsw only if it
can explicitly prove that the increment operation won't overflow.
Apart from the attached test case, another (more realistic)
manifestation of the bug can be seen in
Transforms/IndVarSimplify/pr20680.ll.
Differential Revision: http://reviews.llvm.org/D7778
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230533 91177308-0d34-0410-b5e6-96231b3b80d8
123 lines
4.7 KiB
LLVM
123 lines
4.7 KiB
LLVM
; RUN: opt < %s -loop-reduce -S | FileCheck %s
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; LSR shouldn't consider %t8 to be an interesting user of %t6, and it
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; should be able to form pretty GEPs.
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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define void @Z4() nounwind {
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; CHECK-LABEL: define void @Z4(
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bb:
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br label %bb3
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bb1: ; preds = %bb3
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br i1 undef, label %bb10, label %bb2
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bb2: ; preds = %bb1
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%t = add i64 %t4, 1 ; <i64> [#uses=1]
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br label %bb3
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bb3: ; preds = %bb2, %bb
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%t4 = phi i64 [ %t, %bb2 ], [ 0, %bb ] ; <i64> [#uses=3]
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br label %bb1
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; CHECK: bb10:
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; CHECK-NEXT: %t7 = icmp eq i64 %t4, 0
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; Host %t2 computation outside the loop.
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; CHECK-NEXT: [[SCEVGEP:%[^ ]+]] = getelementptr i8* undef, i64 %t4
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; CHECK-NEXT: br label %bb14
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bb10: ; preds = %bb9
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%t7 = icmp eq i64 %t4, 0 ; <i1> [#uses=1]
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%t3 = add i64 %t4, 16 ; <i64> [#uses=1]
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br label %bb14
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; CHECK: bb14:
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; CHECK-NEXT: store i8 undef, i8* [[SCEVGEP]]
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; CHECK-NEXT: %t6 = load float** undef
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; Fold %t3's add within the address.
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; CHECK-NEXT: [[SCEVGEP1:%[^ ]+]] = getelementptr float* %t6, i64 4
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; CHECK-NEXT: [[SCEVGEP2:%[^ ]+]] = bitcast float* [[SCEVGEP1]] to i8*
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; Use the induction variable (%t4) to access the right element
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; CHECK-NEXT: [[ADDRESS:%[^ ]+]] = getelementptr i8* [[SCEVGEP2]], i64 %t4
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; CHECK-NEXT: store i8 undef, i8* [[ADDRESS]]
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; CHECK-NEXT: br label %bb14
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bb14: ; preds = %bb14, %bb10
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%t2 = getelementptr inbounds i8* undef, i64 %t4 ; <i8*> [#uses=1]
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store i8 undef, i8* %t2
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%t6 = load float** undef
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%t8 = bitcast float* %t6 to i8* ; <i8*> [#uses=1]
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%t9 = getelementptr inbounds i8* %t8, i64 %t3 ; <i8*> [#uses=1]
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store i8 undef, i8* %t9
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br label %bb14
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}
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define fastcc void @TransformLine() nounwind {
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; CHECK-LABEL: @TransformLine(
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bb:
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br label %loop0
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; CHECK: loop0:
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; Induction variable is initialized to -2.
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; CHECK-NEXT: [[PHIIV:%[^ ]+]] = phi i32 [ [[IVNEXT:%[^ ]+]], %loop0 ], [ -2, %bb ]
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; CHECK-NEXT: [[IVNEXT]] = add nuw nsw i32 [[PHIIV]], 1
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; CHECK-NEXT: br i1 false, label %loop0, label %bb0
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loop0: ; preds = %loop0, %bb
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%i0 = phi i32 [ %i0.next, %loop0 ], [ 0, %bb ] ; <i32> [#uses=2]
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%i0.next = add i32 %i0, 1 ; <i32> [#uses=1]
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br i1 false, label %loop0, label %bb0
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bb0: ; preds = %loop0
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br label %loop1
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; CHECK: loop1:
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; CHECK-NEXT: %i1 = phi i32 [ 0, %bb0 ], [ %i1.next, %bb5 ]
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; IVNEXT covers the uses of %i0 and %t0.
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; Therefore, %t0 has been removed.
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; The critical edge has been split.
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; CHECK-NEXT: br i1 false, label %bb2, label %[[LOOP1BB6:.+]]
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loop1: ; preds = %bb5, %bb0
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%i1 = phi i32 [ 0, %bb0 ], [ %i1.next, %bb5 ] ; <i32> [#uses=4]
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%t0 = add i32 %i0, %i1 ; <i32> [#uses=1]
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br i1 false, label %bb2, label %bb6
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; CHECK: bb2:
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; Critical edge split.
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; CHECK-NEXT: br i1 true, label %[[BB2BB6:[^,]+]], label %bb5
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bb2: ; preds = %loop1
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br i1 true, label %bb6, label %bb5
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; CHECK: bb5:
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; CHECK-NEXT: %i1.next = add i32 %i1, 1
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; CHECK-NEXT: br i1 true, label %[[BB5BB6:[^,]+]], label %loop1
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bb5: ; preds = %bb2
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%i1.next = add i32 %i1, 1 ; <i32> [#uses=1]
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br i1 true, label %bb6, label %loop1
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; bb5 to bb6 split basic block.
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; CHECK: [[BB5BB6]]:
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; CHECK-NEXT: [[INITIALVAL:%[^ ]+]] = add i32 [[IVNEXT]], %i1.next
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; CHECK-NEXT: br label %[[SPLITTOBB6:.+]]
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; bb2 to bb6 split basic block.
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; CHECK: [[BB2BB6]]:
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; CHECK-NEXT: br label %[[SPLITTOBB6]]
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; Split basic blocks to bb6.
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; CHECK: [[SPLITTOBB6]]:
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; CHECK-NEXT: [[INITP8:%[^ ]+]] = phi i32 [ [[INITIALVAL]], %[[BB5BB6]] ], [ undef, %[[BB2BB6]] ]
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; CHECK-NEXT: [[INITP9:%[^ ]+]] = phi i32 [ undef, %[[BB5BB6]] ], [ %i1, %[[BB2BB6]] ]
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; CHECK-NEXT: br label %bb6
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; CHECK: [[LOOP1BB6]]:
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; CHECK-NEXT: br label %bb6
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; CHECK: bb6:
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; CHECK-NEXT: %p8 = phi i32 [ undef, %[[LOOP1BB6]] ], [ [[INITP8]], %[[SPLITTOBB6]] ]
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; CHECK-NEXT: %p9 = phi i32 [ %i1, %[[LOOP1BB6]] ], [ [[INITP9]], %[[SPLITTOBB6]] ]
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; CHECK-NEXT: unreachable
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bb6: ; preds = %bb5, %bb2, %loop1
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%p8 = phi i32 [ %t0, %bb5 ], [ undef, %loop1 ], [ undef, %bb2 ] ; <i32> [#uses=0]
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%p9 = phi i32 [ undef, %bb5 ], [ %i1, %loop1 ], [ %i1, %bb2 ] ; <i32> [#uses=0]
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unreachable
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}
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