mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-01 00:11:00 +00:00
27a08935ca
overhead: Merge 3 parallel vectors into 1, change regsUsed hash_set to be a
bitvector. Sped up LLC a little less than 10% in a debug build!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4261 91177308-0d34-0410-b5e6-96231b3b80d8
576 lines
18 KiB
C++
576 lines
18 KiB
C++
//===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
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//
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// This file contains the declaration of the MachineInstr class, which is the
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// basic representation for all target dependant machine instructions used by
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// the back end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_MACHINEINSTR_H
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#define LLVM_CODEGEN_MACHINEINSTR_H
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#include "llvm/Target/MachineInstrInfo.h"
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#include "llvm/Annotation.h"
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#include <Support/iterator>
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class Instruction;
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//---------------------------------------------------------------------------
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// class MachineOperand
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//
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// Purpose:
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// Representation of each machine instruction operand.
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// This class is designed so that you can allocate a vector of operands
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// first and initialize each one later.
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//
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// E.g, for this VM instruction:
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// ptr = alloca type, numElements
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// we generate 2 machine instructions on the SPARC:
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//
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// mul Constant, Numelements -> Reg
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// add %sp, Reg -> Ptr
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//
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// Each instruction has 3 operands, listed above. Of those:
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// - Reg, NumElements, and Ptr are of operand type MO_Register.
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// - Constant is of operand type MO_SignExtendedImmed on the SPARC.
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//
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// For the register operands, the virtual register type is as follows:
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//
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// - Reg will be of virtual register type MO_MInstrVirtualReg. The field
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// MachineInstr* minstr will point to the instruction that computes reg.
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//
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// - %sp will be of virtual register type MO_MachineReg.
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// The field regNum identifies the machine register.
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//
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// - NumElements will be of virtual register type MO_VirtualReg.
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// The field Value* value identifies the value.
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//
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// - Ptr will also be of virtual register type MO_VirtualReg.
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// Again, the field Value* value identifies the value.
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//
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//---------------------------------------------------------------------------
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class MachineOperand {
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public:
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enum MachineOperandType {
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MO_VirtualRegister, // virtual register for *value
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MO_MachineRegister, // pre-assigned machine register `regNum'
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MO_CCRegister,
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MO_SignExtendedImmed,
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MO_UnextendedImmed,
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MO_PCRelativeDisp,
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};
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private:
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// Bit fields of the flags variable used for different operand properties
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static const char DEFFLAG = 0x1; // this is a def of the operand
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static const char DEFUSEFLAG = 0x2; // this is both a def and a use
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static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
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static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
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static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
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static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
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private:
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union {
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Value* value; // BasicBlockVal for a label operand.
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// ConstantVal for a non-address immediate.
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// Virtual register for an SSA operand,
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// including hidden operands required for
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// the generated machine code.
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int64_t immedVal; // constant value for an explicit constant
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};
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MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
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char flags; // see bit field definitions above
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int regNum; // register number for an explicit register
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// will be set for a value after reg allocation
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public:
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/*ctor*/ MachineOperand ();
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/*ctor*/ MachineOperand (MachineOperandType operandType,
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Value* _val);
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/*copy ctor*/ MachineOperand (const MachineOperand&);
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/*dtor*/ ~MachineOperand () {}
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// Accessor methods. Caller is responsible for checking the
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// operand type before invoking the corresponding accessor.
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//
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inline MachineOperandType getOperandType() const {
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return opType;
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}
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inline Value* getVRegValue () const {
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assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_PCRelativeDisp);
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return value;
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}
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inline Value* getVRegValueOrNull() const {
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return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_PCRelativeDisp)? value : NULL;
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}
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inline int getMachineRegNum() const {
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assert(opType == MO_MachineRegister);
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return regNum;
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}
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inline int64_t getImmedValue () const {
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assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
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return immedVal;
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}
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inline bool opIsDef () const {
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return flags & DEFFLAG;
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}
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inline bool opIsDefAndUse () const {
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return flags & DEFUSEFLAG;
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}
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inline bool opHiBits32 () const {
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return flags & HIFLAG32;
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}
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inline bool opLoBits32 () const {
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return flags & LOFLAG32;
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}
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inline bool opHiBits64 () const {
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return flags & HIFLAG64;
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}
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inline bool opLoBits64 () const {
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return flags & LOFLAG64;
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}
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// used to check if a machine register has been allocated to this operand
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inline bool hasAllocatedReg() const {
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return (regNum >= 0 &&
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(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_MachineRegister));
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}
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// used to get the reg number if when one is allocated
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inline int getAllocatedRegNum() const {
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assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_MachineRegister);
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return regNum;
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}
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public:
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friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
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private:
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// These functions are provided so that a vector of operands can be
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// statically allocated and individual ones can be initialized later.
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// Give class MachineInstr access to these functions.
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//
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void Initialize (MachineOperandType operandType,
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Value* _val);
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void InitializeConst (MachineOperandType operandType,
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int64_t intValue);
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void InitializeReg (int regNum,
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bool isCCReg);
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// Construction methods needed for fine-grain control.
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// These must be accessed via coresponding methods in MachineInstr.
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void markDef() { flags |= DEFFLAG; }
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void markDefAndUse() { flags |= DEFUSEFLAG; }
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void markHi32() { flags |= HIFLAG32; }
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void markLo32() { flags |= LOFLAG32; }
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void markHi64() { flags |= HIFLAG64; }
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void markLo64() { flags |= LOFLAG64; }
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// Replaces the Value with its corresponding physical register after
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// register allocation is complete
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void setRegForValue(int reg) {
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assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
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opType == MO_MachineRegister);
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regNum = reg;
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}
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friend class MachineInstr;
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};
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inline
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MachineOperand::MachineOperand()
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: immedVal(0), opType(MO_VirtualRegister), flags(0), regNum(-1)
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{}
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inline
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MachineOperand::MachineOperand(MachineOperandType operandType,
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Value* _val)
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: immedVal(0), opType(operandType), flags(0), regNum(-1)
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{}
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inline
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MachineOperand::MachineOperand(const MachineOperand& mo)
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: opType(mo.opType), flags(mo.flags)
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{
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switch(opType) {
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case MO_VirtualRegister:
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case MO_CCRegister: value = mo.value; break;
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case MO_MachineRegister: regNum = mo.regNum; break;
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case MO_SignExtendedImmed:
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case MO_UnextendedImmed:
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case MO_PCRelativeDisp: immedVal = mo.immedVal; break;
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default: assert(0);
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}
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}
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inline void
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MachineOperand::Initialize(MachineOperandType operandType,
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Value* _val)
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{
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opType = operandType;
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value = _val;
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regNum = -1;
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flags = 0;
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}
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inline void
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MachineOperand::InitializeConst(MachineOperandType operandType,
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int64_t intValue)
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{
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opType = operandType;
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value = NULL;
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immedVal = intValue;
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regNum = -1;
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flags = 0;
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}
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inline void
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MachineOperand::InitializeReg(int _regNum, bool isCCReg)
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{
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opType = isCCReg? MO_CCRegister : MO_MachineRegister;
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value = NULL;
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regNum = (int) _regNum;
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flags = 0;
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}
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//---------------------------------------------------------------------------
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// class MachineInstr
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//
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// Purpose:
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// Representation of each machine instruction.
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//
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// MachineOpCode must be an enum, defined separately for each target.
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// E.g., It is defined in SparcInstructionSelection.h for the SPARC.
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//
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// opCodeMask is used to record variants of an instruction.
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// E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
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// ANNUL: if 1: Annul delay slot instruction.
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// PREDICT-NOT-TAKEN: if 1: predict branch not taken.
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// Instead of creating 4 different opcodes for BNZ, we create a single
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// opcode and set bits in opCodeMask for each of these flags.
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//
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// There are 2 kinds of operands:
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//
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// (1) Explicit operands of the machine instruction in vector operands[]
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//
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// (2) "Implicit operands" are values implicitly used or defined by the
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// machine instruction, such as arguments to a CALL, return value of
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// a CALL (if any), and return value of a RETURN.
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//---------------------------------------------------------------------------
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class MachineInstr : public Annotable, // MachineInstrs are annotable
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public NonCopyable { // Disable copy operations
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MachineOpCode opCode; // the opcode
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OpCodeMask opCodeMask; // extra bits for variants of an opcode
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std::vector<MachineOperand> operands; // the operands
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struct ImplicitRef {
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Value *Val;
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bool isDef, isDefAndUse;
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ImplicitRef(Value *V, bool D, bool DU) : Val(V), isDef(D), isDefAndUse(DU){}
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};
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// implicitRefs - Values implicitly referenced by this machine instruction
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// (eg, call args)
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std::vector<ImplicitRef> implicitRefs;
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// regsUsed - all machine registers used for this instruction, including regs
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// used to save values across the instruction. This is a bitset of registers.
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std::vector<bool> regsUsed;
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public:
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/*ctor*/ MachineInstr (MachineOpCode _opCode,
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OpCodeMask _opCodeMask = 0x0);
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/*ctor*/ MachineInstr (MachineOpCode _opCode,
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unsigned numOperands,
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OpCodeMask _opCodeMask = 0x0);
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inline ~MachineInstr () {}
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//
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// Support to rewrite a machine instruction in place: for now, simply
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// replace() and then set new operands with Set.*Operand methods below.
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//
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void replace (MachineOpCode _opCode,
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unsigned numOperands,
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OpCodeMask _opCodeMask = 0x0);
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//
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// The op code. Note that MachineOpCode is a target-specific type.
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//
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const MachineOpCode getOpCode () const { return opCode; }
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//
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// Information about explicit operands of the instruction
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//
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unsigned int getNumOperands () const { return operands.size(); }
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bool operandIsDefined(unsigned i) const;
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bool operandIsDefinedAndUsed(unsigned i) const;
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const MachineOperand& getOperand (unsigned i) const;
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MachineOperand& getOperand (unsigned i);
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//
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// Information about implicit operands of the instruction
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//
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unsigned getNumImplicitRefs() const{ return implicitRefs.size();}
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bool implicitRefIsDefined(unsigned i) const;
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bool implicitRefIsDefinedAndUsed(unsigned i) const;
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const Value* getImplicitRef (unsigned i) const;
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Value* getImplicitRef (unsigned i);
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//
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// Information about registers used in this instruction
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//
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const std::vector<bool> &getRegsUsed () const { return regsUsed; }
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// insertUsedReg - Add a register to the Used registers set...
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void insertUsedReg(unsigned Reg) {
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if (Reg >= regsUsed.size())
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regsUsed.resize(Reg+1);
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regsUsed[Reg] = true;
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}
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//
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// Debugging support
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//
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void dump () const;
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friend std::ostream& operator<< (std::ostream& os,
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const MachineInstr& minstr);
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//
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// Define iterators to access the Value operands of the Machine Instruction.
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// begin() and end() are defined to produce these iterators...
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//
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template<class _MI, class _V> class ValOpIterator;
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typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
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typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
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// Access to set the operands when building the machine instruction
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//
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void SetMachineOperandVal(unsigned i,
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MachineOperand::MachineOperandType
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operandType,
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Value* _val,
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bool isDef=false,
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bool isDefAndUse=false);
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void SetMachineOperandConst(unsigned i,
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MachineOperand::MachineOperandType
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operandType,
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int64_t intValue);
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void SetMachineOperandReg(unsigned i, int regNum,
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bool isDef=false,
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bool isDefAndUse=false,
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bool isCCReg=false);
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void addImplicitRef (Value* val,
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bool isDef=false,
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bool isDefAndUse=false);
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void setImplicitRef (unsigned i,
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Value* val,
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bool isDef=false,
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bool isDefAndUse=false);
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unsigned substituteValue (const Value* oldVal,
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Value* newVal,
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bool defsOnly = true);
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void setOperandHi32 (unsigned i);
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void setOperandLo32 (unsigned i);
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void setOperandHi64 (unsigned i);
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void setOperandLo64 (unsigned i);
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// Replaces the Value for the operand with its allocated
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// physical register after register allocation is complete.
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//
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void SetRegForOperand(unsigned i, int regNum);
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//
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// Iterator to enumerate machine operands.
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//
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template<class MITy, class VTy>
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class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
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unsigned i;
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MITy MI;
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inline void skipToNextVal() {
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while (i < MI->getNumOperands() &&
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!((MI->getOperand(i).getOperandType() == MachineOperand::MO_VirtualRegister ||
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MI->getOperand(i).getOperandType() == MachineOperand::MO_CCRegister)
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&& MI->getOperand(i).getVRegValue() != 0))
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++i;
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}
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inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
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skipToNextVal();
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}
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public:
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typedef ValOpIterator<MITy, VTy> _Self;
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inline VTy operator*() const {
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return MI->getOperand(i).getVRegValue();
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}
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const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
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MachineOperand &getMachineOperand() { return MI->getOperand(i);}
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inline VTy operator->() const { return operator*(); }
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inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
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inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
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inline _Self& operator++() { i++; skipToNextVal(); return *this; }
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inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
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inline bool operator==(const _Self &y) const {
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return i == y.i;
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}
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inline bool operator!=(const _Self &y) const {
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return !operator==(y);
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}
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static _Self begin(MITy MI) {
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return _Self(MI, 0);
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}
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static _Self end(MITy MI) {
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return _Self(MI, MI->getNumOperands());
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}
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};
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// define begin() and end()
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val_op_iterator begin() { return val_op_iterator::begin(this); }
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val_op_iterator end() { return val_op_iterator::end(this); }
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const_val_op_iterator begin() const {
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return const_val_op_iterator::begin(this);
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}
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const_val_op_iterator end() const {
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return const_val_op_iterator::end(this);
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}
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};
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inline MachineOperand&
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MachineInstr::getOperand(unsigned int i)
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{
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assert(i < operands.size() && "getOperand() out of range!");
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return operands[i];
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}
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inline const MachineOperand&
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MachineInstr::getOperand(unsigned int i) const
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{
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assert(i < operands.size() && "getOperand() out of range!");
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return operands[i];
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}
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inline bool
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MachineInstr::operandIsDefined(unsigned int i) const
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{
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return getOperand(i).opIsDef();
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}
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inline bool
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MachineInstr::operandIsDefinedAndUsed(unsigned int i) const
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{
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return getOperand(i).opIsDefAndUse();
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}
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inline bool
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MachineInstr::implicitRefIsDefined(unsigned i) const
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{
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assert(i < implicitRefs.size() && "operand out of range!");
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return implicitRefs[i].isDef;
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}
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inline bool
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MachineInstr::implicitRefIsDefinedAndUsed(unsigned i) const
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{
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assert(i < implicitRefs.size() && "operand out of range!");
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return implicitRefs[i].isDefAndUse;
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}
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inline const Value*
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MachineInstr::getImplicitRef(unsigned i) const
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{
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assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
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return implicitRefs[i].Val;
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}
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inline Value*
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MachineInstr::getImplicitRef(unsigned i)
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{
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assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
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return implicitRefs[i].Val;
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}
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inline void
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MachineInstr::addImplicitRef(Value* val,
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bool isDef,
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bool isDefAndUse) {
|
|
implicitRefs.push_back(ImplicitRef(val, isDef, isDefAndUse));
|
|
}
|
|
|
|
inline void
|
|
MachineInstr::setImplicitRef(unsigned int i,
|
|
Value* val,
|
|
bool isDef,
|
|
bool isDefAndUse)
|
|
{
|
|
assert(i < implicitRefs.size() && "setImplicitRef() out of range!");
|
|
implicitRefs[i].Val = val;
|
|
implicitRefs[i].isDef = isDef;
|
|
implicitRefs[i].isDefAndUse = isDefAndUse;
|
|
}
|
|
|
|
inline void
|
|
MachineInstr::setOperandHi32(unsigned i)
|
|
{
|
|
operands[i].markHi32();
|
|
}
|
|
|
|
inline void
|
|
MachineInstr::setOperandLo32(unsigned i)
|
|
{
|
|
operands[i].markLo32();
|
|
}
|
|
|
|
inline void
|
|
MachineInstr::setOperandHi64(unsigned i)
|
|
{
|
|
operands[i].markHi64();
|
|
}
|
|
|
|
inline void
|
|
MachineInstr::setOperandLo64(unsigned i)
|
|
{
|
|
operands[i].markLo64();
|
|
}
|
|
|
|
|
|
//---------------------------------------------------------------------------
|
|
// Debugging Support
|
|
//---------------------------------------------------------------------------
|
|
|
|
std::ostream& operator<< (std::ostream& os, const MachineInstr& minstr);
|
|
|
|
std::ostream& operator<< (std::ostream& os, const MachineOperand& mop);
|
|
|
|
void PrintMachineInstructions(const Function *F);
|
|
|
|
#endif
|