llvm-6502/test/CodeGen
Tom Stellard 8eaed0f63d R600/SI: Change all instruction assembly names to lowercase.
This matches the format produced by the AMD proprietary driver.

//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
   you want to convert to this script as arguments).
//==================================================================//

; This was necessary on my system so that A-Z in sed would match only
; upper case.  I'm not sure why.
export LC_ALL='C'

TEST_FILES="$*"

MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`

for f in $TEST_FILES; do
  # Check that there are SI tests:
  grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
  if [ $? -eq 0 ]; then
    for match in $MATCHES; do
      sed -i -e "s/\([ :]$match\)/\L\1/" $f
    done

    # Try to get check lines with partial instruction names
    sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
  fi
done

sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll

//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//

export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
2014-11-05 14:50:53 +00:00
..
AArch64 [AArch64] Use the correct register class for ORR. 2014-11-04 22:20:07 +00:00
ARM ARM: try to add extra CS-register whenever stack alignment >= 8. 2014-11-05 00:27:20 +00:00
CPP
Generic Revert "Revert "DI: Fold constant arguments into a single MDString"" 2014-10-03 20:01:09 +00:00
Hexagon Handle ctor/init_array initialization. 2014-11-03 14:56:05 +00:00
Inputs Revert "Revert "DI: Fold constant arguments into a single MDString"" 2014-10-03 20:01:09 +00:00
Mips Revert "[mips] Add names and tests for the hardware registers" 2014-11-04 22:15:05 +00:00
MSP430 Drop the W postfix on the 16-bit registers. 2014-09-10 06:58:14 +00:00
NVPTX [NVPTX] aligned byte-buffers for vector return types 2014-10-25 03:46:16 +00:00
PowerPC [PowerPC] Initial VSX intrinsic support, with min/max for vector double 2014-10-31 19:19:07 +00:00
R600 R600/SI: Change all instruction assembly names to lowercase. 2014-11-05 14:50:53 +00:00
SPARC Add back tests for empty function in SPARC and PowerPC. 2014-09-15 22:11:07 +00:00
SystemZ
Thumb Improve logic that decides if its profitable to commute when some of the virtual registers involved have uses/defs chains connecting them to physical register. Fix up the tests that this change improves. 2014-11-05 06:43:02 +00:00
Thumb2 ARM: Fix a bug which was causing convergence failure in constant-island pass. 2014-10-17 01:31:47 +00:00
X86 [X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks. 2014-11-05 13:04:14 +00:00
XCore Fix a bit of confusion about .set and produce more readable assembly. 2014-10-21 01:17:30 +00:00