mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
140 lines
5.1 KiB
LLVM
140 lines
5.1 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI --check-prefix=FUNC %s
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; RUN: llc < %s -march=r600 -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=CI --check-prefix=FUNC %s
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; On Southern Islands GPUs the local address space(3) uses 32-bit pointers and
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; the global address space(1) uses 64-bit pointers. These tests check to make sure
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; the correct pointer size is used for the local address space.
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; The e{{32|64}} suffix on the instructions refers to the encoding size and not
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; the size of the operands. The operand size is denoted in the instruction name.
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; Instructions with B32, U32, and I32 in their name take 32-bit operands, while
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; instructions with B64, U64, and I64 take 64-bit operands.
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; FUNC-LABEL: {{^}}local_address_load:
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; CHECK: v_mov_b32_e{{32|64}} [[PTR:v[0-9]]]
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; CHECK: ds_read_b32 v{{[0-9]+}}, [[PTR]]
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define void @local_address_load(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
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entry:
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%0 = load i32 addrspace(3)* %in
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store i32 %0, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_address_gep:
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; CHECK: s_add_i32 [[SPTR:s[0-9]]]
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; CHECK: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
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; CHECK: ds_read_b32 [[VPTR]]
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define void @local_address_gep(i32 addrspace(1)* %out, i32 addrspace(3)* %in, i32 %offset) {
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entry:
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%0 = getelementptr i32 addrspace(3)* %in, i32 %offset
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%1 = load i32 addrspace(3)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_address_gep_const_offset:
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; CHECK: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
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; CHECK: ds_read_b32 v{{[0-9]+}}, [[VPTR]], 0x4,
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define void @local_address_gep_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
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entry:
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%0 = getelementptr i32 addrspace(3)* %in, i32 1
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%1 = load i32 addrspace(3)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; Offset too large, can't fold into 16-bit immediate offset.
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; FUNC-LABEL: {{^}}local_address_gep_large_const_offset:
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; CHECK: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
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; CHECK: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
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; CHECK: ds_read_b32 [[VPTR]]
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define void @local_address_gep_large_const_offset(i32 addrspace(1)* %out, i32 addrspace(3)* %in) {
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entry:
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%0 = getelementptr i32 addrspace(3)* %in, i32 16385
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%1 = load i32 addrspace(3)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}null_32bit_lds_ptr:
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; CHECK: v_cmp_ne_i32
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; CHECK-NOT: v_cmp_ne_i32
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; CHECK: V_CNDMASK_B32
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define void @null_32bit_lds_ptr(i32 addrspace(1)* %out, i32 addrspace(3)* %lds) nounwind {
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%cmp = icmp ne i32 addrspace(3)* %lds, null
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%x = select i1 %cmp, i32 123, i32 456
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store i32 %x, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}mul_32bit_ptr:
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; CHECK: v_mul_lo_i32
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; CHECK-NEXT: v_add_i32_e32
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; CHECK-NEXT: ds_read_b32
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define void @mul_32bit_ptr(float addrspace(1)* %out, [3 x float] addrspace(3)* %lds, i32 %tid) {
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%ptr = getelementptr [3 x float] addrspace(3)* %lds, i32 %tid, i32 0
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%val = load float addrspace(3)* %ptr
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store float %val, float addrspace(1)* %out
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ret void
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}
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@g_lds = addrspace(3) global float zeroinitializer, align 4
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; FUNC-LABEL: {{^}}infer_ptr_alignment_global_offset:
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; CHECK: v_mov_b32_e32 [[REG:v[0-9]+]], 0
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; CHECK: ds_read_b32 v{{[0-9]+}}, [[REG]]
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define void @infer_ptr_alignment_global_offset(float addrspace(1)* %out, i32 %tid) {
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%val = load float addrspace(3)* @g_lds
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store float %val, float addrspace(1)* %out
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ret void
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}
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@ptr = addrspace(3) global i32 addrspace(3)* null
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@dst = addrspace(3) global [16384 x i32] zeroinitializer
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; FUNC-LABEL: {{^}}global_ptr:
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; CHECK: ds_write_b32
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define void @global_ptr() nounwind {
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store i32 addrspace(3)* getelementptr ([16384 x i32] addrspace(3)* @dst, i32 0, i32 16), i32 addrspace(3)* addrspace(3)* @ptr
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ret void
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}
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; FUNC-LABEL: {{^}}local_address_store:
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; CHECK: ds_write_b32
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define void @local_address_store(i32 addrspace(3)* %out, i32 %val) {
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store i32 %val, i32 addrspace(3)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}local_address_gep_store:
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; CHECK: s_add_i32 [[SADDR:s[0-9]+]],
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; CHECK: v_mov_b32_e32 [[ADDR:v[0-9]+]], [[SADDR]]
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; CHECK: ds_write_b32 [[ADDR]], v{{[0-9]+}},
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define void @local_address_gep_store(i32 addrspace(3)* %out, i32, i32 %val, i32 %offset) {
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%gep = getelementptr i32 addrspace(3)* %out, i32 %offset
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store i32 %val, i32 addrspace(3)* %gep, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}local_address_gep_const_offset_store:
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; CHECK: v_mov_b32_e32 [[VPTR:v[0-9]+]], s{{[0-9]+}}
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; CHECK: v_mov_b32_e32 [[VAL:v[0-9]+]], s{{[0-9]+}}
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; CHECK: ds_write_b32 [[VPTR]], [[VAL]], 0x4
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define void @local_address_gep_const_offset_store(i32 addrspace(3)* %out, i32 %val) {
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%gep = getelementptr i32 addrspace(3)* %out, i32 1
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store i32 %val, i32 addrspace(3)* %gep, align 4
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ret void
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}
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; Offset too large, can't fold into 16-bit immediate offset.
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; FUNC-LABEL: {{^}}local_address_gep_large_const_offset_store:
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; CHECK: s_add_i32 [[SPTR:s[0-9]]], s{{[0-9]+}}, 0x10004
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; CHECK: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[SPTR]]
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; CHECK: ds_write_b32 [[VPTR]], v{{[0-9]+}}, 0
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define void @local_address_gep_large_const_offset_store(i32 addrspace(3)* %out, i32 %val) {
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%gep = getelementptr i32 addrspace(3)* %out, i32 16385
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store i32 %val, i32 addrspace(3)* %gep, align 4
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ret void
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}
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