mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
98 lines
3.1 KiB
LLVM
98 lines
3.1 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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declare double @fabs(double) readnone
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declare double @llvm.fabs.f64(double) readnone
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declare <2 x double> @llvm.fabs.v2f64(<2 x double>) readnone
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declare <4 x double> @llvm.fabs.v4f64(<4 x double>) readnone
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; FUNC-LABEL: {{^}}v_fabs_f64:
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; SI: v_and_b32
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; SI: s_endpgm
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define void @v_fabs_f64(double addrspace(1)* %out, double addrspace(1)* %in) {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%tidext = sext i32 %tid to i64
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%gep = getelementptr double addrspace(1)* %in, i64 %tidext
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%val = load double addrspace(1)* %gep, align 8
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%fabs = call double @llvm.fabs.f64(double %val)
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store double %fabs, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fabs_f64:
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; SI: v_and_b32
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; SI-NOT: v_and_b32
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; SI: s_endpgm
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define void @fabs_f64(double addrspace(1)* %out, double %in) {
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%fabs = call double @llvm.fabs.f64(double %in)
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store double %fabs, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fabs_v2f64:
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; SI: v_and_b32
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; SI: v_and_b32
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; SI: s_endpgm
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define void @fabs_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %in) {
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%fabs = call <2 x double> @llvm.fabs.v2f64(<2 x double> %in)
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store <2 x double> %fabs, <2 x double> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fabs_v4f64:
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; SI: v_and_b32
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; SI: v_and_b32
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; SI: v_and_b32
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; SI: v_and_b32
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; SI: s_endpgm
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define void @fabs_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %in) {
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%fabs = call <4 x double> @llvm.fabs.v4f64(<4 x double> %in)
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store <4 x double> %fabs, <4 x double> addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}fabs_fold_f64:
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; SI: s_load_dwordx2 [[ABS_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-NOT: and
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; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, |[[ABS_VALUE]]|, {{v\[[0-9]+:[0-9]+\]}}
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; SI: s_endpgm
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define void @fabs_fold_f64(double addrspace(1)* %out, double %in0, double %in1) {
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%fabs = call double @llvm.fabs.f64(double %in0)
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%fmul = fmul double %fabs, %in1
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store double %fmul, double addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}fabs_fn_fold_f64:
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; SI: s_load_dwordx2 [[ABS_VALUE:s\[[0-9]+:[0-9]+\]]], {{s\[[0-9]+:[0-9]+\]}}, 0xb
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; SI-NOT: and
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; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\]}}, |[[ABS_VALUE]]|, {{v\[[0-9]+:[0-9]+\]}}
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; SI: s_endpgm
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define void @fabs_fn_fold_f64(double addrspace(1)* %out, double %in0, double %in1) {
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%fabs = call double @fabs(double %in0)
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%fmul = fmul double %fabs, %in1
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store double %fmul, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fabs_free_f64:
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; SI: v_and_b32
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; SI: s_endpgm
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define void @fabs_free_f64(double addrspace(1)* %out, i64 %in) {
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%bc= bitcast i64 %in to double
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%fabs = call double @llvm.fabs.f64(double %bc)
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store double %fabs, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fabs_fn_free_f64:
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; SI: v_and_b32
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; SI: s_endpgm
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define void @fabs_fn_free_f64(double addrspace(1)* %out, i64 %in) {
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%bc= bitcast i64 %in to double
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%fabs = call double @fabs(double %bc)
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store double %fabs, double addrspace(1)* %out
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ret void
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}
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