mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 02:29:22 +00:00
d72ba1af57
Summary: The 64-bit version of the variable shift instructions uses the shift_rotate_reg class which uses a GPR32Opnd to specify the variable shift amount. With this patch we avoid the generation of a redundant SLL instruction for the variable shift instructions in 64-bit targets. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7413 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235376 91177308-0d34-0410-b5e6-96231b3b80d8
107 lines
2.0 KiB
LLVM
107 lines
2.0 KiB
LLVM
; RUN: llc -march=mips64el -mcpu=mips64r2 < %s | FileCheck %s
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define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: dsllv
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%shl = shl i64 %a0, %a1
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ret i64 %shl
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}
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define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: dsrav
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%shr = ashr i64 %a0, %a1
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ret i64 %shr
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}
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define i64 @f2(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK: dsrlv
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%shr = lshr i64 %a0, %a1
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ret i64 %shr
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}
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define i64 @f3(i64 %a0) nounwind readnone {
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entry:
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; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10
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%shl = shl i64 %a0, 10
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ret i64 %shl
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}
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define i64 @f4(i64 %a0) nounwind readnone {
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entry:
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; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10
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%shr = ashr i64 %a0, 10
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ret i64 %shr
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}
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define i64 @f5(i64 %a0) nounwind readnone {
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entry:
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; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10
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%shr = lshr i64 %a0, 10
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ret i64 %shr
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}
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define i64 @f6(i64 %a0) nounwind readnone {
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entry:
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; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 40
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%shl = shl i64 %a0, 40
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ret i64 %shl
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}
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define i64 @f7(i64 %a0) nounwind readnone {
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entry:
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; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 40
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%shr = ashr i64 %a0, 40
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ret i64 %shr
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}
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define i64 @f8(i64 %a0) nounwind readnone {
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entry:
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; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 40
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%shr = lshr i64 %a0, 40
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ret i64 %shr
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}
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define i64 @f9(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK-NOT: sll
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; CHECK: drotrv
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%shr = lshr i64 %a0, %a1
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%sub = sub i64 64, %a1
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%shl = shl i64 %a0, %sub
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%or = or i64 %shl, %shr
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ret i64 %or
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}
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define i64 @f10(i64 %a0, i64 %a1) nounwind readnone {
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entry:
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; CHECK-NOT: sll
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; CHECK: drotrv
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%shl = shl i64 %a0, %a1
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%sub = sub i64 64, %a1
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%shr = lshr i64 %a0, %sub
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%or = or i64 %shr, %shl
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ret i64 %or
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}
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define i64 @f11(i64 %a0) nounwind readnone {
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entry:
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; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 10
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%shr = lshr i64 %a0, 10
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%shl = shl i64 %a0, 54
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%or = or i64 %shr, %shl
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ret i64 %or
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}
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define i64 @f12(i64 %a0) nounwind readnone {
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entry:
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; CHECK: drotr ${{[0-9]+}}, ${{[0-9]+}}, 54
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%shl = shl i64 %a0, 10
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%shr = lshr i64 %a0, 54
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%or = or i64 %shl, %shr
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ret i64 %or
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}
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