Jim Grosbach 7032f922b1 Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos ...

and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116534 91177308-0d34-0410-b5e6-96231b3b80d8

2010-10-14 22:57:13 +00:00

..

Alpha

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ARM

Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos

2010-10-14 22:57:13 +00:00

Blackfin

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CBackend

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CellSPU

Zap some redundant 'ori $?, $?, 0' from SPU.

2010-10-01 09:20:01 +00:00

CPP

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Generic

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MBlaze

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Mips

Enable machine sinking critical edge splitting. e.g.

2010-09-20 22:52:00 +00:00

MSP430

CombinerAA is now reordering these stores.

2010-09-20 20:56:29 +00:00

PowerPC

PowerPC varargs functions store live-in registers on the stack. Make sure we use

2010-10-11 20:43:09 +00:00

PTX

Add test case for PTX ret instruction

2010-09-25 07:49:54 +00:00

SPARC

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SystemZ

Correct bogus module triple specifications.

2010-08-30 10:48:29 +00:00

Thumb

Try again to disable critical edge splitting in CodeGenPrepare.

2010-09-30 20:51:52 +00:00

Thumb2

Change register allocation order for ARM VFP and NEON registers to put the

2010-10-08 06:15:13 +00:00

X86

Fix another case where we were preferring instructions with large

2010-10-13 17:14:25 +00:00

XCore

Enable machine sinking critical edge splitting. e.g.

2010-09-20 22:52:00 +00:00

thumb2-mul.ll

Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes

2010-09-21 22:51:46 +00:00