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6762d91c05
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76612 91177308-0d34-0410-b5e6-96231b3b80d8
37 lines
1.3 KiB
TableGen
37 lines
1.3 KiB
TableGen
//===- ARMSchedule.td - ARM Scheduling Definitions ---------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Functional units across ARM processors
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//
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def FU_iALU : FuncUnit; // Integer alu unit
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def FU_iLdSt : FuncUnit; // Integer load / store unit
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def FU_FpALU : FuncUnit; // FP alu unit
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def FU_FpLdSt : FuncUnit; // FP load / store unit
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def FU_Br : FuncUnit; // Branch unit
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary classes used for ARM
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//
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def IIC_iALU : InstrItinClass;
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def IIC_iLoad : InstrItinClass;
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def IIC_iStore : InstrItinClass;
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def IIC_fpALU : InstrItinClass;
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def IIC_fpLoad : InstrItinClass;
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def IIC_fpStore : InstrItinClass;
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def IIC_Br : InstrItinClass;
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//===----------------------------------------------------------------------===//
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// Processor instruction itineraries.
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def GenericItineraries : ProcessorItineraries<[]>;
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include "ARMScheduleV6.td"
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include "ARMScheduleV7.td"
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