Johnny Chen 9091bf25d9 T2 Load/Store Multiple: ... These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128240 91177308-0d34-0410-b5e6-96231b3b80d8		2011-03-24 21:36:56 +00:00
..
arm-tests.txt	ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder was fooled.	2011-03-24 20:42:48 +00:00
dg.exp
invalid-CPS3p-arm.txt	Plug a leak in the arm disassembler and put the tests back.	2011-03-24 21:14:28 +00:00
invalid-VLDMSDB-arm.txt	Plug a leak in the arm disassembler and put the tests back.	2011-03-24 21:14:28 +00:00
neon-tests.txt	The r118201 added support for VORR (immediate). Update ARMDisassemblerCore.cpp to disassemble the	2011-03-24 18:40:38 +00:00
thumb-tests.txt	T2 Load/Store Multiple:	2011-03-24 21:36:56 +00:00