Oliver Stannard ff18b9ff38 [ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM) ... The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be modelled using the same target feature, and all double-precision operations are already disabled by the fp-only-sp target features. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218747 91177308-0d34-0410-b5e6-96231b3b80d8		2014-10-01 09:02:17 +00:00
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Analysis	[BasicAA] Make better use of zext and sign information	2014-09-30 22:43:40 +00:00
Assembler
Bindings
Bitcode
BugPoint
CodeGen	[ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM)	2014-10-01 09:02:17 +00:00
DebugInfo	test: XFAIL the non-darwin gmlt test on darwin	2014-10-01 05:45:45 +00:00
ExecutionEngine
Feature
FileCheck
Instrumentation
Integer
JitListener
Linker
LTO
MC	[mips] Fix disassembly of [ls][wd]c[23], cache, and pref	2014-10-01 08:26:55 +00:00
Object
Other
TableGen
tools
Transforms	[InstCombine] Optimize icmp-select-icmp	2014-10-01 00:13:22 +00:00
Unit
Verifier
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg
lit.site.cfg.in
Makefile
Makefile.tests
TestRunner.sh