Oliver Stannard ff18b9ff38 [ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM) ... The Cortex-M7 has 3 options for its FPU: none, FPv5-SP-D16 and FPv5-DP-D16. FPv5 has the same instructions as FP-ARMv8, so it can be modelled using the same target feature, and all double-precision operations are already disabled by the fp-only-sp target features. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218747 91177308-0d34-0410-b5e6-96231b3b80d8		2014-10-01 09:02:17 +00:00
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AArch64	Recommit r218010 [FastISel][AArch64] Fold bit test and branch into TBZ and TBNZ.	2014-09-30 19:59:35 +00:00
ARM	[ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM)	2014-10-01 09:02:17 +00:00
CPP
Generic
Hexagon	Add missing attributes !cmp.[eq,gt,gtu] instructions.	2014-09-25 13:09:54 +00:00
Inputs
Mips	[mips] For indirect calls we don't need $gp to point to .got. Mips linker	2014-10-01 08:22:21 +00:00
MSP430
NVPTX
PowerPC	Refactor reciprocal and reciprocal square root estimate into target-independent functions (part 2).	2014-09-26 23:01:47 +00:00
R600	R600/SI: Fix printing of clamp and omod	2014-09-30 19:49:48 +00:00
SPARC
SystemZ
Thumb
Thumb2	[ARM] Add support for Cortex-M7, FPv5-SP and FPv5-DP (LLVM)	2014-10-01 09:02:17 +00:00
X86	[x86] Teach the new vector shuffle lowering to be even more aggressive	2014-10-01 03:19:43 +00:00
XCore