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Unfortunately, even with the workaround of disabling the linker TLS optimizations in Clang restored (which has already been done), this still breaks self-hosting on my P7 machine (-O3 -DNDEBUG -mcpu=native). Bill is currently working on an alternate implementation to address the TLS issue in a way that also fully elides the linker bug (which, unfortunately, this approach did not fully), so I'm reverting this now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228460 91177308-0d34-0410-b5e6-96231b3b80d8
287 lines
9.3 KiB
C++
287 lines
9.3 KiB
C++
//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Top-level implementation for the PowerPC target.
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//
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//===----------------------------------------------------------------------===//
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#include "PPCTargetMachine.h"
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#include "PPC.h"
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#include "PPCTargetObjectFile.h"
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#include "PPCTargetTransformInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Function.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Transforms/Scalar.h"
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using namespace llvm;
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static cl::
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opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
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cl::desc("Disable CTR loops for PPC"));
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static cl::
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opt<bool> DisablePreIncPrep("disable-ppc-preinc-prep", cl::Hidden,
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cl::desc("Disable PPC loop preinc prep"));
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static cl::opt<bool>
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VSXFMAMutateEarly("schedule-ppc-vsx-fma-mutation-early",
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cl::Hidden, cl::desc("Schedule VSX FMA instruction mutation early"));
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static cl::opt<bool>
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EnableGEPOpt("ppc-gep-opt", cl::Hidden,
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cl::desc("Enable optimizations on complex GEPs"),
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cl::init(true));
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extern "C" void LLVMInitializePowerPCTarget() {
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// Register the targets
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RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
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RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
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RegisterTargetMachine<PPC64TargetMachine> C(ThePPC64LETarget);
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}
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/// Return the datalayout string of a subtarget.
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static std::string getDataLayoutString(const Triple &T) {
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bool is64Bit = T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le;
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std::string Ret;
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// Most PPC* platforms are big endian, PPC64LE is little endian.
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if (T.getArch() == Triple::ppc64le)
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Ret = "e";
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else
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Ret = "E";
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Ret += DataLayout::getManglingComponent(T);
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// PPC32 has 32 bit pointers. The PS3 (OS Lv2) is a PPC64 machine with 32 bit
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// pointers.
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if (!is64Bit || T.getOS() == Triple::Lv2)
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Ret += "-p:32:32";
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// Note, the alignment values for f64 and i64 on ppc64 in Darwin
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// documentation are wrong; these are correct (i.e. "what gcc does").
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if (is64Bit || !T.isOSDarwin())
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Ret += "-i64:64";
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else
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Ret += "-f64:32:64";
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// PPC64 has 32 and 64 bit registers, PPC32 has only 32 bit ones.
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if (is64Bit)
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Ret += "-n32:64";
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else
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Ret += "-n32";
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return Ret;
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}
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static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, StringRef TT) {
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std::string FullFS = FS;
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Triple TargetTriple(TT);
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// Make sure 64-bit features are available when CPUname is generic
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if (TargetTriple.getArch() == Triple::ppc64 ||
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TargetTriple.getArch() == Triple::ppc64le) {
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if (!FullFS.empty())
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FullFS = "+64bit," + FullFS;
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else
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FullFS = "+64bit";
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}
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if (OL >= CodeGenOpt::Default) {
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if (!FullFS.empty())
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FullFS = "+crbits," + FullFS;
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else
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FullFS = "+crbits";
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}
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if (OL != CodeGenOpt::None) {
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if (!FullFS.empty())
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FullFS = "+invariant-function-descriptors," + FullFS;
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else
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FullFS = "+invariant-function-descriptors";
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}
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return FullFS;
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}
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static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
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// If it isn't a Mach-O file then it's going to be a linux ELF
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// object file.
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if (TT.isOSDarwin())
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return make_unique<TargetLoweringObjectFileMachO>();
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return make_unique<PPC64LinuxTargetObjectFile>();
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}
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// The FeatureString here is a little subtle. We are modifying the feature string
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// with what are (currently) non-function specific overrides as it goes into the
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// LLVMTargetMachine constructor and then using the stored value in the
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// Subtarget constructor below it.
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PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, TT, CPU, computeFSAdditions(FS, OL, TT), Options, RM,
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CM, OL),
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TLOF(createTLOF(Triple(getTargetTriple()))),
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DL(getDataLayoutString(Triple(TT))), Subtarget(TT, CPU, TargetFS, *this) {
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initAsmInfo();
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}
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PPCTargetMachine::~PPCTargetMachine() {}
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void PPC32TargetMachine::anchor() { }
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PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
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}
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void PPC64TargetMachine::anchor() { }
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PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {
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}
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const PPCSubtarget *
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PPCTargetMachine::getSubtargetImpl(const Function &F) const {
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AttributeSet FnAttrs = F.getAttributes();
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Attribute CPUAttr =
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FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-cpu");
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Attribute FSAttr =
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FnAttrs.getAttribute(AttributeSet::FunctionIndex, "target-features");
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std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
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? CPUAttr.getValueAsString().str()
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: TargetCPU;
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std::string FS = !FSAttr.hasAttribute(Attribute::None)
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? FSAttr.getValueAsString().str()
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: TargetFS;
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auto &I = SubtargetMap[CPU + FS];
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if (!I) {
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// This needs to be done before we create a new subtarget since any
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// creation will depend on the TM and the code generation flags on the
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// function that reside in TargetOptions.
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resetTargetOptions(F);
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I = llvm::make_unique<PPCSubtarget>(TargetTriple, CPU, FS, *this);
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}
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return I.get();
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}
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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namespace {
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/// PPC Code Generator Pass Configuration Options.
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class PPCPassConfig : public TargetPassConfig {
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public:
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PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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PPCTargetMachine &getPPCTargetMachine() const {
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return getTM<PPCTargetMachine>();
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}
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void addIRPasses() override;
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bool addPreISel() override;
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bool addILPOpts() override;
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bool addInstSelector() override;
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void addPreRegAlloc() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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};
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} // namespace
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TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new PPCPassConfig(this, PM);
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}
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void PPCPassConfig::addIRPasses() {
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addPass(createAtomicExpandPass(&getPPCTargetMachine()));
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if (TM->getOptLevel() == CodeGenOpt::Aggressive && EnableGEPOpt) {
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// Call SeparateConstOffsetFromGEP pass to extract constants within indices
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// and lower a GEP with multiple indices to either arithmetic operations or
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// multiple GEPs with single index.
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addPass(createSeparateConstOffsetFromGEPPass(TM, true));
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// Call EarlyCSE pass to find and remove subexpressions in the lowered
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// result.
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addPass(createEarlyCSEPass());
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// Do loop invariant code motion in case part of the lowered result is
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// invariant.
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addPass(createLICMPass());
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}
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TargetPassConfig::addIRPasses();
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}
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bool PPCPassConfig::addPreISel() {
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if (!DisablePreIncPrep && getOptLevel() != CodeGenOpt::None)
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addPass(createPPCLoopPreIncPrepPass(getPPCTargetMachine()));
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if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
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addPass(createPPCCTRLoops(getPPCTargetMachine()));
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return false;
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}
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bool PPCPassConfig::addILPOpts() {
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addPass(&EarlyIfConverterID);
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return true;
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}
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bool PPCPassConfig::addInstSelector() {
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// Install an instruction selector.
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addPass(createPPCISelDag(getPPCTargetMachine()));
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#ifndef NDEBUG
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if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
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addPass(createPPCCTRLoopsVerify());
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#endif
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addPass(createPPCVSXCopyPass());
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return false;
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}
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void PPCPassConfig::addPreRegAlloc() {
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initializePPCVSXFMAMutatePass(*PassRegistry::getPassRegistry());
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insertPass(VSXFMAMutateEarly ? &RegisterCoalescerID : &MachineSchedulerID,
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&PPCVSXFMAMutateID);
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}
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void PPCPassConfig::addPreSched2() {
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if (getOptLevel() != CodeGenOpt::None)
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addPass(&IfConverterID);
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}
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void PPCPassConfig::addPreEmitPass() {
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if (getOptLevel() != CodeGenOpt::None)
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addPass(createPPCEarlyReturnPass(), false);
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// Must run branch selection immediately preceding the asm printer.
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addPass(createPPCBranchSelectionPass(), false);
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}
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TargetIRAnalysis PPCTargetMachine::getTargetIRAnalysis() {
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return TargetIRAnalysis(
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[this](Function &F) { return TargetTransformInfo(PPCTTIImpl(this, F)); });
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}
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