llvm-6502/test/CodeGen/Thumb2/thumb2-ror.ll
Joerg Sonnenberger aca2998f14 Enabling thumb2 mode used to force support for armv6t2. Replace this
with a temporary assertion and adjust the various test cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197224 91177308-0d34-0410-b5e6-96231b3b80d8
2013-12-13 11:16:00 +00:00

27 lines
582 B
LLVM

; RUN: llc < %s -march=thumb -mcpu=arm1156t2-s -mattr=+thumb2 | FileCheck %s
; RUN: llc < %s -march=thumb | FileCheck %s -check-prefix=THUMB1
; CHECK-LABEL: f1:
; CHECK: ror.w r0, r0, #22
define i32 @f1(i32 %a) {
%l8 = shl i32 %a, 10
%r8 = lshr i32 %a, 22
%tmp = or i32 %l8, %r8
ret i32 %tmp
}
; CHECK-LABEL: f2:
; CHECK-NOT: and
; CHECK: ror
; THUMB1: f2
; THUMB1: and
define i32 @f2(i32 %v, i32 %nbits) {
entry:
%and = and i32 %nbits, 31
%shr = lshr i32 %v, %and
%sub = sub i32 32, %and
%shl = shl i32 %v, %sub
%or = or i32 %shl, %shr
ret i32 %or
}