Hal Finkel 75dd57a8f0 Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handling ... There are a couple of (small) related changes here: 1. The printed name of the VRSAVE register has been changed from VRsave to vrsave in order to match the name accepted by GNU binutils. 2. Support for parsing vrsave has been added to the asm parser (it seems that there was no test case specifically covering this code, so I've added one). 3. The list of Altivec registers, which was common to all calling conventions, has been separated out. This allows us to define the base CSR lists, and then lists for each ABI with Altivec included. This allows SjLj, for example, to work correctly on non-Altivec targets without using unnatural definitions of the NoRegs CSR list. 4. VRSAVE is now always reserved on non-Darwin targets and all Altivec registers are reserved when Altivec is disabled. With these changes, it is now possible to compile a function containing __builtin_unwind_init() on Linux/PPC64 with debugging information. This did not work previously because GNU binutils assumes that all .cfi_offset offsets will be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned offset). This is not true for the vrsave register, however, because this register is used only on Darwin, GCC does not bother printing a .cfi_offset entry for it (even though there is a slot in the stack frame for it as specified by the ABI). This change allows us to do the same: we will also not print .cfi_offset directives for vrsave. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185409 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-02 03:39:34 +00:00
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lit.local.cfg
ppc64-encoding-bookII.s	[PowerPC] Also add "msync" alias	2013-07-01 20:39:50 +00:00
ppc64-encoding-ext.s	[PowerPC] Support all condition register logical instructions	2013-07-01 21:40:54 +00:00
ppc64-encoding-fp.s	[PowerPC] Add assembler parser	2013-05-03 19:49:39 +00:00
ppc64-encoding-vmx.s	[PowerPC] Add assembler parser	2013-05-03 19:49:39 +00:00
ppc64-encoding.s	[PowerPC] Support all condition register logical instructions	2013-07-01 21:40:54 +00:00
ppc64-errors.s	[PowerPC] Accept 17-bit signed immediates for addis	2013-06-26 13:49:53 +00:00
ppc64-fixup-apply.s	[PowerPC] Support @higher et.al. modifiers	2013-06-21 14:43:42 +00:00
ppc64-fixup-explicit.s	[PowerPC] Fix @got references to local symbols	2013-07-01 18:19:56 +00:00
ppc64-fixups.s	[PowerPC] Add support for TLS data relocations	2013-07-01 23:33:29 +00:00
ppc64-initial-cfa.s	[MC/DWARF] Support .debug_frame / .debug_line code alignment factors	2013-06-12 14:46:54 +00:00
ppc64-operands.s	[PowerPC] Accept 17-bit signed immediates for addis	2013-06-26 13:49:53 +00:00
ppc64-regs.s	Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handling	2013-07-02 03:39:34 +00:00
ppc64-relocs-01.s	[PowerPC] Use assembler source in MC tests	2013-06-12 14:14:18 +00:00
ppc64-tls-relocs-01.s	[PowerPC] Use assembler source in MC tests	2013-06-12 14:14:18 +00:00