Chris Lattner 919c032fa4 Modify the ppc backend to use two register classes for FP: F8RC and F4RC. ... These are used to represent float and double values, and the two regclasses contain the same physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23577 91177308-0d34-0410-b5e6-96231b3b80d8		2005-10-01 01:35:02 +00:00
..
Alpha	subtarget support for CIX and FIX extentions (the only 2 I care about right now)	2005-09-30 20:24:38 +00:00
CBackend	fix CBackend/2005-09-27-VolatileFuncPtr.ll	2005-09-27 20:52:44 +00:00
IA64	these registers don't belong to any register classes, so don't mark them	2005-09-30 06:42:24 +00:00
PowerPC	Modify the ppc backend to use two register classes for FP: F8RC and F4RC.	2005-10-01 01:35:02 +00:00
Skeleton	CR registers are not used by this "target"	2005-09-30 06:43:58 +00:00
Sparc	Pass extra regclasses into spilling code	2005-09-30 01:29:42 +00:00
SparcV8	Pass extra regclasses into spilling code	2005-09-30 01:29:42 +00:00
SparcV9	Rename MRegisterDesc -> TargetRegisterDesc for consistency	2005-09-30 17:49:27 +00:00
X86	simplify this code using the new regclass info passed in	2005-09-30 17:12:38 +00:00
Makefile
MRegisterInfo.cpp	Rename MRegisterDesc -> TargetRegisterDesc for consistency	2005-09-30 17:49:27 +00:00
SubtargetFeature.cpp	Print:	2005-09-07 05:44:14 +00:00
Target.td	Now that self referential classes are supported, get rid of a work-around.	2005-09-30 04:13:23 +00:00
TargetData.cpp
TargetFrameInfo.cpp
TargetInstrInfo.cpp
TargetMachine.cpp
TargetMachineRegistry.cpp	1. Use SubtargetFeatures in llc/lli.	2005-09-01 21:38:21 +00:00
TargetSchedInfo.cpp
TargetSubtarget.cpp