Vincent Lejeune 91ec4b0cac R600: fix swizzle export ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192553 91177308-0d34-0410-b5e6-96231b3b80d8		2013-10-13 17:56:04 +00:00
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AArch64	Implement aarch64 neon instruction set AdvSIMD (copy).	2013-10-11 02:33:55 +00:00
ARM	Remove kill flags after if conversion if necessary	2013-10-11 19:04:37 +00:00
CPP
Generic
Hexagon
Inputs
Mips	For Mips16, start to consolidate all forms of 32 bit literal loading so that	2013-10-12 02:19:08 +00:00
MSP430
NVPTX	[NVPTX] Switch from StrongPHIElimination to PHIElimination in NVPTXTargetMachine, and add some missing optimization passes to addOptimizedRegAlloc	2013-10-11 12:39:39 +00:00
PowerPC
R600	R600: fix swizzle export	2013-10-13 17:56:04 +00:00
SPARC	[Sparc] Disable tail call optimization for sparc64.	2013-10-09 12:50:39 +00:00
SystemZ
Thumb
Thumb2
X86	Force a CPU on test so it doesn't depend on microarchitectural scheduling decisions.	2013-10-12 11:17:12 +00:00
XCore	XCore target fix bug in emitArrayBound() causing segmentation fault	2013-10-11 10:27:13 +00:00