mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-12 00:29:20 +00:00
9367b8d4f2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179420 91177308-0d34-0410-b5e6-96231b3b80d8
120 lines
3.1 KiB
LLVM
120 lines
3.1 KiB
LLVM
; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s -check-prefix=R1
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; RUN: llc -march=mips -mattr=dspr2 < %s | FileCheck %s -check-prefix=R2
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; R1: test_lbux:
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; R1: lbux ${{[0-9]+}}
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define zeroext i8 @test_lbux(i8* nocapture %b, i32 %i) {
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entry:
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%add.ptr = getelementptr inbounds i8* %b, i32 %i
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%0 = load i8* %add.ptr, align 1
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ret i8 %0
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}
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; R1: test_lhx:
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; R1: lhx ${{[0-9]+}}
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define signext i16 @test_lhx(i16* nocapture %b, i32 %i) {
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entry:
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%add.ptr = getelementptr inbounds i16* %b, i32 %i
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%0 = load i16* %add.ptr, align 2
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ret i16 %0
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}
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; R1: test_lwx:
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; R1: lwx ${{[0-9]+}}
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define i32 @test_lwx(i32* nocapture %b, i32 %i) {
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entry:
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%add.ptr = getelementptr inbounds i32* %b, i32 %i
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%0 = load i32* %add.ptr, align 4
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ret i32 %0
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}
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; R1: test_add_v2q15_:
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; R1: addq.ph ${{[0-9]+}}
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define { i32 } @test_add_v2q15_(i32 %a.coerce, i32 %b.coerce) {
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entry:
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%0 = bitcast i32 %a.coerce to <2 x i16>
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%1 = bitcast i32 %b.coerce to <2 x i16>
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%add = add <2 x i16> %0, %1
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%2 = bitcast <2 x i16> %add to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
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ret { i32 } %.fca.0.insert
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}
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; R1: test_sub_v2q15_:
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; R1: subq.ph ${{[0-9]+}}
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define { i32 } @test_sub_v2q15_(i32 %a.coerce, i32 %b.coerce) {
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entry:
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%0 = bitcast i32 %a.coerce to <2 x i16>
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%1 = bitcast i32 %b.coerce to <2 x i16>
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%sub = sub <2 x i16> %0, %1
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%2 = bitcast <2 x i16> %sub to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
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ret { i32 } %.fca.0.insert
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}
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; R2: test_mul_v2q15_:
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; R2: mul.ph ${{[0-9]+}}
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; mul.ph is an R2 instruction. Check that multiply node gets expanded.
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; R1: test_mul_v2q15_:
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; R1: mul ${{[0-9]+}}
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; R1: mul ${{[0-9]+}}
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define { i32 } @test_mul_v2q15_(i32 %a.coerce, i32 %b.coerce) {
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entry:
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%0 = bitcast i32 %a.coerce to <2 x i16>
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%1 = bitcast i32 %b.coerce to <2 x i16>
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%mul = mul <2 x i16> %0, %1
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%2 = bitcast <2 x i16> %mul to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
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ret { i32 } %.fca.0.insert
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}
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; R1: test_add_v4i8_:
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; R1: addu.qb ${{[0-9]+}}
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define { i32 } @test_add_v4i8_(i32 %a.coerce, i32 %b.coerce) {
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entry:
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%0 = bitcast i32 %a.coerce to <4 x i8>
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%1 = bitcast i32 %b.coerce to <4 x i8>
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%add = add <4 x i8> %0, %1
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%2 = bitcast <4 x i8> %add to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
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ret { i32 } %.fca.0.insert
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}
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; R1: test_sub_v4i8_:
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; R1: subu.qb ${{[0-9]+}}
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define { i32 } @test_sub_v4i8_(i32 %a.coerce, i32 %b.coerce) {
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entry:
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%0 = bitcast i32 %a.coerce to <4 x i8>
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%1 = bitcast i32 %b.coerce to <4 x i8>
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%sub = sub <4 x i8> %0, %1
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%2 = bitcast <4 x i8> %sub to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
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ret { i32 } %.fca.0.insert
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}
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; DSP-ASE doesn't have a v4i8 multiply instruction. Check that multiply node gets expanded.
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; R2: test_mul_v4i8_:
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; R2: mul ${{[0-9]+}}
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; R2: mul ${{[0-9]+}}
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; R2: mul ${{[0-9]+}}
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; R2: mul ${{[0-9]+}}
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define { i32 } @test_mul_v4i8_(i32 %a.coerce, i32 %b.coerce) {
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entry:
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%0 = bitcast i32 %a.coerce to <4 x i8>
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%1 = bitcast i32 %b.coerce to <4 x i8>
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%mul = mul <4 x i8> %0, %1
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%2 = bitcast <4 x i8> %mul to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
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ret { i32 } %.fca.0.insert
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}
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