Jyotsna Verma 86df21767a Hexagon: Add patterns for zero extended loads from i1->i64. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176689 91177308-0d34-0410-b5e6-96231b3b80d8

2013-03-08 14:15:15 +00:00

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InstPrinter

Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.

2013-02-20 16:13:27 +00:00

MCTargetDesc

Hexagon: Add constant extender support framework.

2013-03-01 17:37:13 +00:00

TargetInfo

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CMakeLists.txt

Extend Hexagon hardware loop generation to handle various additional cases:

2013-02-11 21:37:55 +00:00

Hexagon.h

Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.

2013-02-20 16:13:27 +00:00

Hexagon.td

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HexagonAsmPrinter.cpp

Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.

2013-02-20 16:13:27 +00:00

HexagonAsmPrinter.h

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HexagonCallingConv.td

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HexagonCallingConvLower.cpp

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HexagonCallingConvLower.h

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HexagonCFGOptimizer.cpp

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HexagonExpandPredSpillCode.cpp

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HexagonFixupHwLoops.cpp

Extend Hexagon hardware loop generation to handle various additional cases:

2013-02-11 21:37:55 +00:00

HexagonFrameLowering.cpp

Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo

2013-02-21 20:05:00 +00:00

HexagonFrameLowering.h

Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo

2013-02-21 20:05:00 +00:00

HexagonHardwareLoops.cpp

Extend Hexagon hardware loop generation to handle various additional cases:

2013-02-11 21:37:55 +00:00

HexagonInstrFormats.td

Hexagon: Change insn class to support instruction encoding.

2013-02-14 19:57:17 +00:00

HexagonInstrFormatsV4.td

Hexagon: Change insn class to support instruction encoding.

2013-02-14 19:57:17 +00:00

HexagonInstrInfo.cpp

Hexagon: Use MO operand flags to mark constant extended instructions.

2013-03-05 18:51:42 +00:00

HexagonInstrInfo.h

Hexagon: Use MO operand flags to mark constant extended instructions.

2013-03-05 18:51:42 +00:00

HexagonInstrInfo.td

Hexagon: Add patterns for zero extended loads from i1->i64.

2013-03-08 14:15:15 +00:00

HexagonInstrInfoV3.td

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HexagonInstrInfoV4.td

Hexagon: Add patterns for zero extended loads from i1->i64.

2013-03-08 14:15:15 +00:00

HexagonInstrInfoV5.td

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HexagonIntrinsics.td

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HexagonIntrinsicsDerived.td

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HexagonIntrinsicsV3.td

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HexagonIntrinsicsV4.td

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HexagonIntrinsicsV5.td

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HexagonISelDAGToDAG.cpp

Hexagon: Use absolute addressing mode loads/stores for global+offset

2013-02-13 21:38:46 +00:00

HexagonISelLowering.cpp

Hexagon: Handle i8, i16 and i1 Var Args.

2013-03-07 20:28:34 +00:00

HexagonISelLowering.h

Hexagon: Add support to lower block address.

2013-03-07 19:10:28 +00:00

HexagonMachineFunctionInfo.h

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HexagonMachineScheduler.cpp

Added FIXME for future Hexagon cleanup.

2013-03-02 01:43:08 +00:00

HexagonMachineScheduler.h

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HexagonMCInst.h

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HexagonMCInstLower.cpp

Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h.

2013-02-20 16:13:27 +00:00

HexagonNewValueJump.cpp

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HexagonOperands.td

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HexagonPeephole.cpp

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HexagonRegisterInfo.cpp

Remove code copied from GenRegisterInfo.inc.

2013-02-22 01:15:08 +00:00

HexagonRegisterInfo.h

Remove code copied from GenRegisterInfo.inc.

2013-02-22 01:15:08 +00:00

HexagonRegisterInfo.td

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HexagonRemoveSZExtArgs.cpp

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HexagonSchedule.td

Hexagon: Change insn class to support instruction encoding.

2013-02-14 19:57:17 +00:00

HexagonScheduleV4.td

Hexagon: Change insn class to support instruction encoding.

2013-02-14 19:57:17 +00:00

HexagonSelectCCInfo.td

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HexagonSelectionDAGInfo.cpp

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HexagonSelectionDAGInfo.h

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HexagonSplitTFRCondSets.cpp

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HexagonSubtarget.cpp

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HexagonSubtarget.h

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HexagonTargetMachine.cpp

Hexagon: Use absolute addressing mode loads/stores for global+offset

2013-02-13 21:38:46 +00:00

HexagonTargetMachine.h

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HexagonTargetObjectFile.cpp

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HexagonTargetObjectFile.h

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HexagonVarargsCallingConvention.h

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HexagonVLIWPacketizer.cpp

Hexagon: Use MO operand flags to mark constant extended instructions.

2013-03-05 18:51:42 +00:00

LLVMBuild.txt

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Makefile

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