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02d937d864
* lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a sequence of a pair of i32->i64 extensions followed by a "bitwise or" into COMBINE_rr. * lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg. * test/CodeGen/Hexagon/union-1.ll: New test. * test/CodeGen/Hexagon/combine_ir.ll: Fix test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8
24 lines
640 B
LLVM
24 lines
640 B
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s
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; CHECK: word
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; CHECK-NOT: combine(#0
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; CHECK: jump bar
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define void @word(i32* nocapture %a) nounwind {
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entry:
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%0 = load i32* %a, align 4, !tbaa !0
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%1 = zext i32 %0 to i64
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%add.ptr = getelementptr inbounds i32* %a, i32 1
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%2 = load i32* %add.ptr, align 4, !tbaa !0
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%3 = zext i32 %2 to i64
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%4 = shl nuw i64 %3, 32
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%ins = or i64 %4, %1
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tail call void @bar(i64 %ins) nounwind
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ret void
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}
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declare void @bar(i64)
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!0 = metadata !{metadata !"int", metadata !1}
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!1 = metadata !{metadata !"omnipotent char", metadata !2}
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!2 = metadata !{metadata !"Simple C/C++ TBAA"}
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