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4b828e6384
GCC 4.0.0 compiler (sometimes incorrectly) warns about under release build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22249 91177308-0d34-0410-b5e6-96231b3b80d8
304 lines
12 KiB
C++
304 lines
12 KiB
C++
//===-- SparcV9CodeEmitter.cpp --------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// SPARC-specific backend for emitting machine code to memory.
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//
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// This module also contains the code for lazily resolving the targets of call
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// instructions, including the callback used to redirect calls to functions for
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// which the code has not yet been generated into the JIT compiler.
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//
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// This file #includes SparcV9GenCodeEmitter.inc, which contains the code for
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// getBinaryCodeForInstr(), a method that converts a MachineInstr into the
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// corresponding binary machine code word.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Constants.h"
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#include "llvm/Function.h"
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#include "llvm/GlobalVariable.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/MachineCodeEmitter.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Support/Debug.h"
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#include "SparcV9Internals.h"
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#include "SparcV9TargetMachine.h"
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#include "SparcV9RegInfo.h"
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#include "SparcV9CodeEmitter.h"
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#include "SparcV9Relocations.h"
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#include "MachineFunctionInfo.h"
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using namespace llvm;
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bool SparcV9TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
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MachineCodeEmitter &MCE) {
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PM.add(new SparcV9CodeEmitter(*this, MCE));
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PM.add(createSparcV9MachineCodeDestructionPass());
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return false;
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}
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SparcV9CodeEmitter::SparcV9CodeEmitter(TargetMachine &tm,
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MachineCodeEmitter &M): TM(tm), MCE(M) {}
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void SparcV9CodeEmitter::emitWord(unsigned Val) {
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MCE.emitWord(Val);
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}
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unsigned
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SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
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MachineInstr &MI) {
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const SparcV9RegInfo &RI = *TM.getRegInfo();
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unsigned regClass = 0, regType = RI.getRegType(fakeReg);
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// At least map fakeReg into its class
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fakeReg = RI.getClassRegNum(fakeReg, regClass);
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switch (regClass) {
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case SparcV9RegInfo::IntRegClassID: {
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// SparcV9 manual, p31
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static const unsigned IntRegMap[] = {
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// "o0", "o1", "o2", "o3", "o4", "o5", "o7",
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8, 9, 10, 11, 12, 13, 15,
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// "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
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16, 17, 18, 19, 20, 21, 22, 23,
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// "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
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24, 25, 26, 27, 28, 29, 30, 31,
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// "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
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0, 1, 2, 3, 4, 5, 6, 7,
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// "o6"
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14
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};
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return IntRegMap[fakeReg];
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break;
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}
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case SparcV9RegInfo::FloatRegClassID: {
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DEBUG(std::cerr << "FP reg: " << fakeReg << "\n");
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if (regType == SparcV9RegInfo::FPSingleRegType) {
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// only numbered 0-31, hence can already fit into 5 bits (and 6)
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DEBUG(std::cerr << "FP single reg, returning: " << fakeReg << "\n");
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} else if (regType == SparcV9RegInfo::FPDoubleRegType) {
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// FIXME: This assumes that we only have 5-bit register fields!
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// From SparcV9 Manual, page 40.
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// The bit layout becomes: b[4], b[3], b[2], b[1], b[5]
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fakeReg |= (fakeReg >> 5) & 1;
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fakeReg &= 0x1f;
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DEBUG(std::cerr << "FP double reg, returning: " << fakeReg << "\n");
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}
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return fakeReg;
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}
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case SparcV9RegInfo::IntCCRegClassID: {
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/* xcc, icc, ccr */
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static const unsigned IntCCReg[] = { 6, 4, 2 };
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assert(fakeReg < sizeof(IntCCReg)/sizeof(IntCCReg[0])
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&& "CC register out of bounds for IntCCReg map");
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DEBUG(std::cerr << "IntCC reg: " << IntCCReg[fakeReg] << "\n");
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return IntCCReg[fakeReg];
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}
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case SparcV9RegInfo::FloatCCRegClassID: {
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/* These are laid out %fcc0 - %fcc3 => 0 - 3, so are correct */
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DEBUG(std::cerr << "FP CC reg: " << fakeReg << "\n");
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return fakeReg;
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}
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case SparcV9RegInfo::SpecialRegClassID: {
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// Currently only "special" reg is %fsr, which is encoded as 1 in
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// instructions and 0 in SparcV9SpecialRegClass.
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static const unsigned SpecialReg[] = { 1 };
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assert(fakeReg < sizeof(SpecialReg)/sizeof(SpecialReg[0])
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&& "Special register out of bounds for SpecialReg map");
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DEBUG(std::cerr << "Special reg: " << SpecialReg[fakeReg] << "\n");
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return SpecialReg[fakeReg];
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}
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default:
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assert(0 && "Invalid unified register number in getRealRegNum");
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return fakeReg;
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}
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}
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int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
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MachineOperand &MO) {
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int64_t rv = 0; // Return value; defaults to 0 for unhandled cases
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// or things that get fixed up later by the JIT.
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if (MO.isPCRelativeDisp() || MO.isGlobalAddress()) {
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DEBUG(std::cerr << "PCRelativeDisp: ");
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Value *V = MO.getVRegValue();
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if (BasicBlock *BB = dyn_cast<BasicBlock>(V)) {
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DEBUG(std::cerr << "Saving reference to BB (VReg)\n");
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unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
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BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
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} else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
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// The real target of the branch is CI = PC + (rv * 4)
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// So undo that: give the instruction (CI - PC) / 4
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rv = (CI->getRawValue() - MCE.getCurrentPCValue()) / 4;
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} else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
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unsigned Reloc = 0;
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if (MI.getOpcode() == V9::CALL) {
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Reloc = V9::reloc_pcrel_call;
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} else if (MI.getOpcode() == V9::SETHI) {
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if (MO.isHiBits64())
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Reloc = V9::reloc_sethi_hh;
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else if (MO.isHiBits32())
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Reloc = V9::reloc_sethi_lm;
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else
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assert(0 && "Unknown relocation!");
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} else if (MI.getOpcode() == V9::ORi) {
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if (MO.isLoBits32())
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Reloc = V9::reloc_or_lo;
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else if (MO.isLoBits64())
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Reloc = V9::reloc_or_hm;
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else
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assert(0 && "Unknown relocation!");
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} else {
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assert(0 && "Unknown relocation!");
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}
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MCE.addRelocation(MachineRelocation(MCE.getCurrentPCOffset(), Reloc, GV));
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rv = 0;
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} else {
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std::cerr << "ERROR: PC relative disp unhandled:" << MO << "\n";
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abort();
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}
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} else if (MO.isRegister() || MO.getType() == MachineOperand::MO_CCRegister)
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{
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// This is necessary because the SparcV9 backend doesn't actually lay out
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// registers in the real fashion -- it skips those that it chooses not to
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// allocate, i.e. those that are the FP, SP, etc.
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unsigned fakeReg = MO.getReg();
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unsigned realRegByClass = getRealRegNum(fakeReg, MI);
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DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => "
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<< realRegByClass << " (LLC: "
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<< TM.getRegInfo()->getUnifiedRegName(fakeReg) << ")\n");
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rv = realRegByClass;
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} else if (MO.isImmediate()) {
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rv = MO.getImmedValue();
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DEBUG(std::cerr << "immed: " << rv << "\n");
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} else if (MO.isMachineBasicBlock()) {
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// Duplicate code of the above case for VirtualRegister, BasicBlock...
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// It should really hit this case, but SparcV9 backend uses VRegs instead
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DEBUG(std::cerr << "Saving reference to MBB\n");
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const BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
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unsigned* CurrPC = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
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BBRefs.push_back(std::make_pair(BB, std::make_pair(CurrPC, &MI)));
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} else if (MO.isExternalSymbol()) {
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// SparcV9 backend doesn't generate this (yet...)
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std::cerr << "ERROR: External symbol unhandled: " << MO << "\n";
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abort();
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} else if (MO.isFrameIndex()) {
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// SparcV9 backend doesn't generate this (yet...)
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int FrameIndex = MO.getFrameIndex();
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std::cerr << "ERROR: Frame index unhandled.\n";
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abort();
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} else if (MO.isConstantPoolIndex()) {
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unsigned Index = MO.getConstantPoolIndex();
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rv = MCE.getConstantPoolEntryAddress(Index);
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} else {
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std::cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
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abort();
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}
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// Finally, deal with the various bitfield-extracting functions that
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// are used in SPARC assembly. (Some of these make no sense in combination
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// with some of the above; we'll trust that the instruction selector
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// will not produce nonsense, and not check for valid combinations here.)
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if (MO.isLoBits32()) { // %lo(val) == %lo() in SparcV9 ABI doc
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return rv & 0x03ff;
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} else if (MO.isHiBits32()) { // %lm(val) == %hi() in SparcV9 ABI doc
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return (rv >> 10) & 0x03fffff;
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} else if (MO.isLoBits64()) { // %hm(val) == %ulo() in SparcV9 ABI doc
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return (rv >> 32) & 0x03ff;
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} else if (MO.isHiBits64()) { // %hh(val) == %uhi() in SparcV9 ABI doc
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return rv >> 42;
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} else { // (unadorned) val
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return rv;
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}
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}
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unsigned SparcV9CodeEmitter::getValueBit(int64_t Val, unsigned bit) {
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Val >>= bit;
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return (Val & 1);
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}
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bool SparcV9CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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MCE.startFunction(MF);
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DEBUG(std::cerr << "Starting function " << MF.getFunction()->getName()
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<< ", address: " << "0x" << std::hex
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<< (long)MCE.getCurrentPCValue() << "\n");
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MCE.emitConstantPool(MF.getConstantPool());
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
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emitBasicBlock(*I);
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MCE.finishFunction(MF);
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DEBUG(std::cerr << "Finishing fn " << MF.getFunction()->getName() << "\n");
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// Resolve branches to BasicBlocks for the entire function
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for (unsigned i = 0, e = BBRefs.size(); i != e; ++i) {
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long Location = BBLocations[BBRefs[i].first];
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unsigned *Ref = BBRefs[i].second.first;
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MachineInstr *MI = BBRefs[i].second.second;
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DEBUG(std::cerr << "Fixup @ " << std::hex << Ref << " to 0x" << Location
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<< " in instr: " << std::dec << *MI);
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for (unsigned ii = 0, ee = MI->getNumOperands(); ii != ee; ++ii) {
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MachineOperand &op = MI->getOperand(ii);
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if (op.isPCRelativeDisp()) {
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// the instruction's branch target is made such that it branches to
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// PC + (branchTarget * 4), so undo that arithmetic here:
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// Location is the target of the branch
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// Ref is the location of the instruction, and hence the PC
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int64_t branchTarget = (Location - (long)Ref) >> 2;
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// Save the flags.
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bool loBits32=false, hiBits32=false, loBits64=false, hiBits64=false;
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if (op.isLoBits32()) { loBits32=true; }
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if (op.isHiBits32()) { hiBits32=true; }
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if (op.isLoBits64()) { loBits64=true; }
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if (op.isHiBits64()) { hiBits64=true; }
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MI->SetMachineOperandConst(ii, MachineOperand::MO_SignExtendedImmed,
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branchTarget);
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if (loBits32) { MI->getOperand(ii).markLo32(); }
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else if (hiBits32) { MI->getOperand(ii).markHi32(); }
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else if (loBits64) { MI->getOperand(ii).markLo64(); }
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else if (hiBits64) { MI->getOperand(ii).markHi64(); }
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DEBUG(std::cerr << "Rewrote BB ref: ");
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unsigned fixedInstr = SparcV9CodeEmitter::getBinaryCodeForInstr(*MI);
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MCE.emitWordAt (fixedInstr, Ref);
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break;
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}
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}
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}
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BBRefs.clear();
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BBLocations.clear();
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return false;
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}
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void SparcV9CodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
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currBB = MBB.getBasicBlock();
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BBLocations[currBB] = MCE.getCurrentPCValue();
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
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if (I->getOpcode() != V9::RDCCR) {
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emitWord(getBinaryCodeForInstr(*I));
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} else {
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// FIXME: The tblgen produced code emitter cannot deal with the fact that
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// machine operand #0 of the RDCCR instruction should be ignored. This is
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// really a bug in the representation of the RDCCR instruction (which has
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// no need to explicitly represent the CCR dest), but we hack around it
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// here.
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unsigned RegNo = getMachineOpValue(*I, I->getOperand(1));
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RegNo &= (1<<5)-1;
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emitWord((RegNo << 25) | 2168487936U);
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}
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}
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#include "SparcV9GenCodeEmitter.inc"
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