Scott Michel 94bd57e154 - Convert remaining i64 custom lowering into custom instruction emission ... sequences in SPUDAGToDAGISel.cpp and SPU64InstrInfo.td, killing custom DAG node types as needed. - i64 mul is now a legal instruction, but emits an instruction sequence that stretches tblgen and the imagination, as well as violating laws of several small countries and most southern US states (just kidding, but looking at a function with 80+ parameters is really weird and just plain wrong.) - Update tests as needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62254 91177308-0d34-0410-b5e6-96231b3b80d8		2009-01-15 04:41:47 +00:00
..
Alpha	Correct some thinkos in the expansion of ADD/SUB	2008-11-12 08:23:26 +00:00
ARM	Clean up some ARM GV asm printing out; minor fixes to match what gcc does.	2008-12-06 02:00:55 +00:00
CBackend	Fix PR2907 by digging through constant expressions to find FP constants that	2008-10-22 04:53:16 +00:00
CellSPU	- Convert remaining i64 custom lowering into custom instruction emission	2009-01-15 04:41:47 +00:00
CPP
Generic	The list-td and list-tdrr schedulers don't yet support physreg	2009-01-13 20:24:13 +00:00
IA64	sabre brings to my attention that the 'tr' suffix is also obsolete	2008-05-20 21:00:03 +00:00
Mips	The list-td and list-tdrr schedulers don't yet support physreg	2009-01-13 20:24:13 +00:00
PowerPC	this test should not run opt -std-compile-opts, it should run	2009-01-09 05:32:00 +00:00
SPARC	Add testcase for 'r' inline asm operand	2008-10-10 20:28:59 +00:00
X86	Disable the register+memory forms of the bt instructions for now. Thanks	2009-01-13 23:23:30 +00:00
XCore	Add pseudo instructions to the XCore for (load|store|load address) of a	2009-01-14 18:26:46 +00:00