mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-19 03:29:22 +00:00
0f3ac8d8d4
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28378 91177308-0d34-0410-b5e6-96231b3b80d8
71 lines
2.6 KiB
TableGen
71 lines
2.6 KiB
TableGen
//===- Alpha.td - Describe the Alpha Target Machine --------*- tablegen -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file was developed by the LLVM research group and is distributed under
|
|
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Get the target-independent interfaces which we are implementing...
|
|
//
|
|
include "../Target.td"
|
|
|
|
//Alpha is little endian
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Subtarget Features
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def FeatureCIX : SubtargetFeature<"CIX", "HasCT", "true",
|
|
"Enable CIX extentions">;
|
|
def FeatureFIX : SubtargetFeature<"FIX", "HasF2I", "true",
|
|
"Enable FIX extentions">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Register File Description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "AlphaRegisterInfo.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Schedule Description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "AlphaSchedule.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction Descriptions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "AlphaInstrInfo.td"
|
|
|
|
def AlphaInstrInfo : InstrInfo {
|
|
// Define how we want to layout our target-specific information field.
|
|
// let TSFlagsFields = [];
|
|
// let TSFlagsShifts = [];
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Alpha Processor Definitions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def : Processor<"generic", Alpha21264Itineraries, []>;
|
|
def : Processor<"pca56" , Alpha21264Itineraries, []>;
|
|
def : Processor<"ev56" , Alpha21264Itineraries, []>;
|
|
def : Processor<"ev6" , Alpha21264Itineraries, [FeatureFIX]>;
|
|
def : Processor<"ev67" , Alpha21264Itineraries, [FeatureFIX, FeatureCIX]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// The Alpha Target
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
def Alpha : Target {
|
|
// Pull in Instruction Info:
|
|
let InstructionSet = AlphaInstrInfo;
|
|
}
|