llvm-6502/lib/CodeGen
Duncan P. N. Exon Smith 95afdd3a07 AsmPrinter: Remove DIEHash::AttrEntry, NFC
Remove "the most boring struct ever" (thanks to review by Eric).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238366 91177308-0d34-0410-b5e6-96231b3b80d8
2015-05-27 22:36:37 +00:00
..
AsmPrinter AsmPrinter: Remove DIEHash::AttrEntry, NFC 2015-05-27 22:36:37 +00:00
MIRParser Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format). 2015-05-27 18:02:19 +00:00
SelectionDAG SelectionDAG: Don't do libcall on div/rem if divrem is custom 2015-05-27 16:54:09 +00:00
AggressiveAntiDepBreaker.cpp
AggressiveAntiDepBreaker.h Test commit: fix typo in comment. 2015-04-22 17:42:37 +00:00
AllocationOrder.cpp
AllocationOrder.h
Analysis.cpp CodeGen: move over-zealous assert into actual if statement. 2015-05-06 20:07:38 +00:00
AntiDepBreaker.h
AtomicExpandPass.cpp Mutate TargetLowering::shouldExpandAtomicRMWInIR to specifically dictate how AtomicRMWInsts are expanded. 2015-03-04 15:47:57 +00:00
BasicTargetTransformInfo.cpp
BranchFolding.cpp MachineInstr: Remove unused parameter. 2015-05-19 21:22:20 +00:00
BranchFolding.h
CalcSpillWeights.cpp
CallingConvLower.cpp
CMakeLists.txt Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format). 2015-05-27 18:02:19 +00:00
CodeGen.cpp [ShrinkWrap] Add (a simplified version) of shrink-wrapping. 2015-05-05 17:38:16 +00:00
CodeGenPrepare.cpp CodeGenPrepare: Don't match addressing modes through addrspacecast 2015-05-26 16:59:43 +00:00
CoreCLRGC.cpp Reformat. 2015-05-25 01:43:34 +00:00
CriticalAntiDepBreaker.cpp
CriticalAntiDepBreaker.h Use 'override/final' instead of 'virtual' for overridden methods 2015-04-11 02:11:45 +00:00
DeadMachineInstructionElim.cpp MachineInstr: Remove unused parameter. 2015-05-19 21:22:20 +00:00
DFAPacketizer.cpp
DwarfEHPrepare.cpp Stop calling DwarfEHPrepare from WinEHPrepare 2015-03-12 00:36:20 +00:00
EarlyIfConversion.cpp MachineInstr: Remove unused parameter. 2015-05-19 21:22:20 +00:00
EdgeBundles.cpp
ErlangGC.cpp
ExecutionDepsFix.cpp remove function names from comments; NFC 2015-03-15 18:16:04 +00:00
ExpandISelPseudos.cpp
ExpandPostRAPseudos.cpp
GCMetadata.cpp Make the message associated with a fatal error slightly more helpful 2015-04-26 22:00:34 +00:00
GCMetadataPrinter.cpp
GCRootLowering.cpp Change Function::getIntrinsicID() to return an Intrinsic::ID. NFC. 2015-05-20 17:16:39 +00:00
GCStrategy.cpp
GlobalMerge.cpp [opaque pointer type] Pass GlobalAlias the actual pointer type rather than decomposing it into pointee type + address space 2015-04-29 21:22:39 +00:00
IfConversion.cpp MachineInstr: Remove unused parameter. 2015-05-19 21:22:20 +00:00
InlineSpiller.cpp [InlineSpiller] Fix rematerialization for bundles. 2015-05-21 21:41:55 +00:00
InterferenceCache.cpp Make static variables const if possible. Makes them go into a read-only section. 2015-03-08 16:07:39 +00:00
InterferenceCache.h Make static variables const if possible. Makes them go into a read-only section. 2015-03-08 16:07:39 +00:00
IntrinsicLowering.cpp
LatencyPriorityQueue.cpp Remove LatencyPriorityQueue::dump because it relies on an implicit copy ctor which is deprecated in C++11 (due to the presence of a user-declare dtor in the base class) 2015-03-03 21:16:56 +00:00
LexicalScopes.cpp IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
LiveDebugVariables.cpp IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
LiveDebugVariables.h IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
LiveInterval.cpp Oops, didn't mean to commit my debug fprintfs 2015-04-08 02:10:01 +00:00
LiveIntervalAnalysis.cpp Do not track subregister liveness when it brings no benefits 2015-03-19 00:21:58 +00:00
LiveIntervalUnion.cpp
LivePhysRegs.cpp Handle dead defs in the if converter. 2015-05-06 22:51:04 +00:00
LiveRangeCalc.cpp LiveRangeCalc: Improve error messages on malformed IR 2015-05-11 18:47:47 +00:00
LiveRangeCalc.h Do not track subregister liveness when it brings no benefits 2015-03-19 00:21:58 +00:00
LiveRangeEdit.cpp MachineInstr: Remove unused parameter. 2015-05-19 21:22:20 +00:00
LiveRegMatrix.cpp
LiveStackAnalysis.cpp Recommit r231168: unique_ptrify LiveRange::segmentSet 2015-03-04 01:20:33 +00:00
LiveVariables.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
LLVMBuild.txt Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format). 2015-05-27 18:02:19 +00:00
LLVMTargetMachine.cpp Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format). 2015-05-27 18:02:19 +00:00
LocalStackSlotAllocation.cpp [ARM] Fix handling of thumb1 out-of-range frame offsets 2015-03-20 17:20:07 +00:00
MachineBasicBlock.cpp MachineBasicBlock: Cleanup computeRegisterLiveness() 2015-05-27 05:12:39 +00:00
MachineBlockFrequencyInfo.cpp
MachineBlockPlacement.cpp [MBP] Spell the conditions the same way through out this if statement. 2015-04-15 13:39:42 +00:00
MachineBranchProbabilityInfo.cpp
MachineCombiner.cpp fix typo in comment; NFC 2015-05-21 21:29:13 +00:00
MachineCopyPropagation.cpp [MachineCopyPropagation] Handle undef flags conservatively so that we do not 2015-04-23 21:17:39 +00:00
MachineCSE.cpp MachineCSE: Add a target query for the LookAheadLimit heurisitic 2015-05-09 00:56:07 +00:00
MachineDominanceFrontier.cpp
MachineDominators.cpp MachineDominators: Move applySplitCriticalEdges into the cpp file. 2015-02-27 23:13:13 +00:00
MachineFunction.cpp MC: Clean up method names in MCContext. 2015-05-18 18:43:14 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp
MachineInstr.cpp MachineInstr: Remove unused parameter. 2015-05-19 21:22:20 +00:00
MachineInstrBundle.cpp
MachineLICM.cpp MachineInstr: Remove unused parameter. 2015-05-19 21:22:20 +00:00
MachineLoopInfo.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
MachineModuleInfo.cpp MC: Clean up method names in MCContext. 2015-05-18 18:43:14 +00:00
MachineModuleInfoImpls.cpp Clear the stub map in getSortedStubs. 2015-04-07 12:59:28 +00:00
MachinePassRegistry.cpp
MachinePostDominators.cpp
MachineRegionInfo.cpp
MachineRegisterInfo.cpp Have TargetRegisterInfo::getLargestLegalSuperClass take a 2015-03-10 23:46:01 +00:00
MachineScheduler.cpp MachineScheduler debug output clarity. 2015-05-17 23:40:31 +00:00
MachineSink.cpp MachineInstr: Remove unused parameter. 2015-05-19 21:22:20 +00:00
MachineSSAUpdater.cpp
MachineTraceMetrics.cpp use range-based for-loops; NFCI 2015-05-21 17:22:45 +00:00
MachineVerifier.cpp MachineInstr: Change return value of getOpcode() to unsigned. 2015-05-18 20:27:55 +00:00
Makefile Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format). 2015-05-27 18:02:19 +00:00
MIRPrintingPass.cpp Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format). 2015-05-27 18:02:19 +00:00
module.modulemap
OcamlGC.cpp
OptimizePHIs.cpp
Passes.cpp [ShrinkWrap] Add (a simplified version) of shrink-wrapping. 2015-05-05 17:38:16 +00:00
PeepholeOptimizer.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
PHIElimination.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp Use 'override/final' instead of 'virtual' for overridden methods 2015-04-11 02:11:45 +00:00
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp MachineInstr: Change return value of getOpcode() to unsigned. 2015-05-18 20:27:55 +00:00
PseudoSourceValue.cpp
README.txt
RegAllocBase.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
RegAllocBase.h
RegAllocBasic.cpp
RegAllocFast.cpp IR: Give 'DI' prefix to debug info metadata 2015-04-29 16:38:44 +00:00
RegAllocGreedy.cpp RegAllocGreedy: Allow target to specify register class ordering. 2015-03-31 19:57:53 +00:00
RegAllocPBQP.cpp [PBQP] Use a local bit-matrix to speedup searching an edge in the graph. 2015-03-05 09:12:59 +00:00
RegisterClassInfo.cpp Have getRegPressureSetLimit take a MachineFunction so that a 2015-03-11 18:34:58 +00:00
RegisterCoalescer.cpp MachineInstr: Remove unused parameter. 2015-05-19 21:22:20 +00:00
RegisterCoalescer.h
RegisterPressure.cpp RegisterPressureTracker: reword stale comments. 2015-05-17 23:40:27 +00:00
RegisterScavenging.cpp
ScheduleDAG.cpp
ScheduleDAGInstrs.cpp use range-based for-loop 2015-05-21 17:04:17 +00:00
ScheduleDAGPrinter.cpp
ScoreboardHazardRecognizer.cpp
ShadowStackGC.cpp
ShadowStackGCLowering.cpp [opaque pointer type] API migration for GEP constant factories 2015-04-02 18:55:32 +00:00
ShrinkWrap.cpp [ShrinkWrap] Add a target hook to check whether or not 2015-05-27 06:25:48 +00:00
SjLjEHPrepare.cpp Simplify IRBuilder::CreateCall* by using ArrayRef+initializer_list/braced init only 2015-05-18 22:13:54 +00:00
SlotIndexes.cpp [llvm] Replacing asserts with static_asserts where appropriate 2015-03-16 09:53:42 +00:00
Spiller.h
SpillPlacement.cpp
SpillPlacement.h Use 'override/final' instead of 'virtual' for overridden methods 2015-04-11 02:11:45 +00:00
SplitKit.cpp
SplitKit.h Fix spelling. 2015-05-02 00:44:07 +00:00
StackColoring.cpp Remove MCInstrItineraries includes in parts that don't use them anymore 2015-05-14 18:01:11 +00:00
StackMapLivenessAnalysis.cpp Internalize the StackMapLiveness pass. 2015-03-24 13:20:54 +00:00
StackMaps.cpp Move alignment from MCSectionData to MCSection. 2015-05-21 19:20:38 +00:00
StackProtector.cpp Simplify IRBuilder::CreateCall* by using ArrayRef+initializer_list/braced init only 2015-05-18 22:13:54 +00:00
StackSlotColoring.cpp Recommit r231175: Change LiveStackAnalysis::SS2IntervalMap from std::map to std::unordered_map 2015-03-04 01:15:53 +00:00
StatepointExampleGC.cpp
TailDuplication.cpp Clear kill flags in tail duplication. 2015-05-07 21:48:26 +00:00
TargetFrameLoweringImpl.cpp Stop resetting NoFramePointerElim in TargetMachine::resetTargetOptions. 2015-05-23 01:14:08 +00:00
TargetInstrInfo.cpp MachineInstr: Change return value of getOpcode() to unsigned. 2015-05-18 20:27:55 +00:00
TargetLoweringBase.cpp Add SDNodes for umin, umax, smin and smax. 2015-05-15 09:03:15 +00:00
TargetLoweringObjectFileImpl.cpp Move alignment from MCSectionData to MCSection. 2015-05-21 19:20:38 +00:00
TargetOptionsImpl.cpp Remove NoFramePointerElim and NoFramePointerElimOverride from TargetOptions and 2015-05-26 20:17:20 +00:00
TargetRegisterInfo.cpp
TargetSchedule.cpp Turn effective assert(0) into llvm_unreachable 2015-05-14 18:33:29 +00:00
TwoAddressInstructionPass.cpp MachineInstr: Remove unused parameter. 2015-05-19 21:22:20 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp Compile time improvements to VirtRegRewriter. 2015-05-22 08:11:26 +00:00
WinEHPrepare.cpp std::sort must be called with a strict weak ordering. 2015-05-21 15:38:25 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.