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https://github.com/c64scene-ar/llvm-6502.git
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b7d0c90c44
wide vectors. Likewise, change VSTn intrinsics to take separate arguments for each vector in a multi-vector struct. Adjust tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77468 91177308-0d34-0410-b5e6-96231b3b80d8
68 lines
2.2 KiB
LLVM
68 lines
2.2 KiB
LLVM
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
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; RUN: grep {vld1\\.8} %t | count 2
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; RUN: grep {vld1\\.16} %t | count 2
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; RUN: grep {vld1\\.32} %t | count 4
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; RUN: grep {vld1\\.64} %t | count 2
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define <8 x i8> @vld1i8(i8* %A) nounwind {
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%tmp1 = call <8 x i8> @llvm.arm.neon.vld1i.v8i8(i8* %A)
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ret <8 x i8> %tmp1
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}
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define <4 x i16> @vld1i16(i16* %A) nounwind {
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%tmp1 = call <4 x i16> @llvm.arm.neon.vld1i.v4i16(i16* %A)
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ret <4 x i16> %tmp1
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}
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define <2 x i32> @vld1i32(i32* %A) nounwind {
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%tmp1 = call <2 x i32> @llvm.arm.neon.vld1i.v2i32(i32* %A)
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ret <2 x i32> %tmp1
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}
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define <2 x float> @vld1f(float* %A) nounwind {
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%tmp1 = call <2 x float> @llvm.arm.neon.vld1f.v2f32(float* %A)
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ret <2 x float> %tmp1
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}
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define <1 x i64> @vld1i64(i64* %A) nounwind {
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%tmp1 = call <1 x i64> @llvm.arm.neon.vld1i.v1i64(i64* %A)
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ret <1 x i64> %tmp1
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}
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define <16 x i8> @vld1Qi8(i8* %A) nounwind {
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%tmp1 = call <16 x i8> @llvm.arm.neon.vld1i.v16i8(i8* %A)
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ret <16 x i8> %tmp1
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}
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define <8 x i16> @vld1Qi16(i16* %A) nounwind {
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%tmp1 = call <8 x i16> @llvm.arm.neon.vld1i.v8i16(i16* %A)
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ret <8 x i16> %tmp1
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}
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define <4 x i32> @vld1Qi32(i32* %A) nounwind {
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%tmp1 = call <4 x i32> @llvm.arm.neon.vld1i.v4i32(i32* %A)
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ret <4 x i32> %tmp1
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}
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define <4 x float> @vld1Qf(float* %A) nounwind {
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%tmp1 = call <4 x float> @llvm.arm.neon.vld1f.v4f32(float* %A)
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ret <4 x float> %tmp1
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}
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define <2 x i64> @vld1Qi64(i64* %A) nounwind {
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%tmp1 = call <2 x i64> @llvm.arm.neon.vld1i.v2i64(i64* %A)
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ret <2 x i64> %tmp1
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}
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declare <8 x i8> @llvm.arm.neon.vld1i.v8i8(i8*) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vld1i.v4i16(i16*) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vld1i.v2i32(i32*) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vld1f.v2f32(float*) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vld1i.v1i64(i64*) nounwind readnone
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declare <16 x i8> @llvm.arm.neon.vld1i.v16i8(i8*) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vld1i.v8i16(i16*) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vld1i.v4i32(i32*) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vld1f.v4f32(float*) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vld1i.v2i64(i64*) nounwind readnone
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