mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-24 23:29:41 +00:00
34ad085eec
Summary: Expand list of supported targets for Mips to include mips32 r1. Previously it only include r2. More patches are coming where there is a difference but in the current patches as pushed upstream, r1 and r2 are equivalent. Test Plan: simplestorefp1.ll add new build bots at mips to test this flavor at both -O0 and -O2 Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5306 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217821 91177308-0d34-0410-b5e6-96231b3b80d8
18 lines
540 B
LLVM
18 lines
540 B
LLVM
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
|
|
; RUN: < %s | FileCheck %s
|
|
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
|
|
; RUN: < %s | FileCheck %s
|
|
|
|
@abcd = external global i32
|
|
|
|
; Function Attrs: nounwind
|
|
define void @foo() {
|
|
entry:
|
|
store i32 12345, i32* @abcd, align 4
|
|
; CHECK: addiu $[[REG1:[0-9]+]], $zero, 12345
|
|
; CHECK: lw $[[REG2:[0-9]+]], %got(abcd)(${{[0-9]+}})
|
|
; CHECK: sw $[[REG1]], 0($[[REG2]])
|
|
ret void
|
|
}
|
|
|