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ARMAddressingModes.h
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Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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2012-02-18 12:03:15 +00:00 |
ARMAsmBackend.cpp
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ARM: Thumb ldr(literal) base address alignment is 32-bits.
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2012-04-26 20:48:12 +00:00 |
ARMBaseInfo.h
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ARM more NEON VLD/VST composite physical register refactoring.
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2012-03-06 23:10:38 +00:00 |
ARMELFObjectWriter.cpp
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Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.
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2012-03-30 09:15:32 +00:00 |
ARMFixupKinds.h
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Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.
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2012-03-30 09:15:32 +00:00 |
ARMMachObjectWriter.cpp
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Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.
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2012-03-30 09:15:32 +00:00 |
ARMMCAsmInfo.cpp
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Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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2012-02-18 12:03:15 +00:00 |
ARMMCAsmInfo.h
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Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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2012-02-18 12:03:15 +00:00 |
ARMMCCodeEmitter.cpp
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Unify internal representation of ARM instructions with a register right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation.
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2012-04-25 18:00:18 +00:00 |
ARMMCExpr.cpp
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Convert assert(0) to llvm_unreachable
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2012-02-07 02:50:20 +00:00 |
ARMMCExpr.h
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Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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2012-02-18 12:03:15 +00:00 |
ARMMCTargetDesc.cpp
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- thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2
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2012-04-27 01:27:19 +00:00 |
ARMMCTargetDesc.h
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If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assume
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2012-04-26 01:13:36 +00:00 |
CMakeLists.txt
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Hopefully fix the cmake build.
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2011-12-22 01:11:01 +00:00 |
LLVMBuild.txt
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LLVMBuild: Remove trailing newline, which irked me.
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2011-12-12 19:48:00 +00:00 |
Makefile
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