Evan Cheng 97b9b97853 PHI elimination should not break back edge. It can cause some significant code placement issues. rdar://8263994 ... good: LBB0_2: mov r2, r0 . . . mov r1, r2 bne LBB0_2 bad: LBB0_2: mov r2, r0 . . . @ BB#3: mov r1, r2 b LBB0_2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111221 91177308-0d34-0410-b5e6-96231b3b80d8		2010-08-17 01:20:36 +00:00
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Alpha
ARM	PHI elimination should not break back edge. It can cause some significant code placement issues. rdar://8263994	2010-08-17 01:20:36 +00:00
Blackfin
CBackend
CellSPU	Have SPU handle halfvec stores aligned by 8 bytes.	2010-08-09 16:33:00 +00:00
CPP
Generic
MBlaze
Mips
MSP430
PIC16
PowerPC
SPARC
SystemZ
Thumb	Fix test and re-enable it.	2010-08-11 17:25:51 +00:00
Thumb2	Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee	2010-08-16 22:26:55 +00:00
X86	PHI elimination should not break back edge. It can cause some significant code placement issues. rdar://8263994	2010-08-17 01:20:36 +00:00
XCore