Richard Osborne 4e3740ee6d Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124587 91177308-0d34-0410-b5e6-96231b3b80d8		2011-01-31 17:41:44 +00:00
..
Alpha
ARM	Add a testcase for my last checkin.	2011-01-27 06:01:17 +00:00
Blackfin
CBackend
CellSPU	Allow sign-extending of i8 and i16 to i128 on SPU.	2011-01-20 15:49:06 +00:00
CPP
Generic	fix rdar://8878965, a regression I introduced with the recent	2011-01-18 20:53:04 +00:00
MBlaze
Mips	Add support for mips32 madd and msub instructions. Patch by Akira Hatanaka	2011-01-18 19:29:17 +00:00
MSP430
PowerPC
PTX
SPARC	Pass sret arguments through the stack instead of through registers in Sparc backend. It makes the code generated more compliant with the sparc32 ABI.	2011-01-22 13:05:16 +00:00
SystemZ
Thumb	Sorry, several patches in one.	2011-01-20 08:34:58 +00:00
Thumb2	Last round of fixes for movw + movt global address codegen.	2011-01-21 18:55:51 +00:00
X86	Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2) when c1 equals the amount of bits that are truncated off.	2011-01-30 16:38:43 +00:00
XCore	Fix bug where ReduceLoadWidth was creating illegal ZEXTLOAD instructions.	2011-01-31 17:41:44 +00:00
thumb2-mul.ll