Andrea Di Biagio 9836c47ea6 [X86] Teach the backend how to fold SSE4.1/AVX/AVX2 blend intrinsics. ... Added target specific combine rules to fold blend intrinsics according to the following rules: 1) fold(blend A, A, Mask) -> A; 2) fold(blend A, B, <allZeros>) -> A; 3) fold(blend A, B, <allOnes>) -> B. Added two new tests to verify that the new folding rules work for all the optimized blend intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208895 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-15 15:18:15 +00:00
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AArch64	ARM64: print correct aliases for NEON mov & mvn instructions	2014-05-15 12:11:02 +00:00
ARM	Rename ComputeMaskedBits to computeKnownBits. "Masked" has been	2014-05-14 21:14:37 +00:00
ARM64	ARM64: print correct aliases for NEON mov & mvn instructions	2014-05-15 12:11:02 +00:00
CPP
Generic
Hexagon	DebugInfo: Sure up subprogram variable list handling with more assertions and fewer conditionals.	2014-05-14 21:52:46 +00:00
Inputs
Mips	Allow sret on the second parameter as well as the first	2014-05-09 22:32:13 +00:00
MSP430
NVPTX
PowerPC	DebugInfo: Sure up subprogram variable list handling with more assertions and fewer conditionals.	2014-05-14 21:52:46 +00:00
R600	R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0	2014-05-15 14:41:54 +00:00
SPARC	Allow sret on the second parameter as well as the first	2014-05-09 22:32:13 +00:00
SystemZ
Thumb
Thumb2
X86	[X86] Teach the backend how to fold SSE4.1/AVX/AVX2 blend intrinsics.	2014-05-15 15:18:15 +00:00
XCore