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llvm-6502/lib/Target/XCore
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Michael Liao a6b20ced76 Fix PR10475 
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands
  but TLI.getShiftAmountTy() so far only return scalar type. As a
  result, backend logic assuming that breaks.
- Rename the original TLI.getShiftAmountTy() to
  TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to
  return target-specificed scalar type or the same vector type as the
  1st operand.
- Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar
  type.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176364 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-01 18:40:30 +00:00
..
Disassembler [XCore] Add missing 2r instructions. 2013-02-17 22:38:05 +00:00
InstPrinter Simplify assertion in XCoreInstPrinter. 2012-12-17 12:13:46 +00:00
MCTargetDesc Resort the #include lines in include/... and lib/... with the 2013-01-02 10:22:59 +00:00
TargetInfo Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
CMakeLists.txt Add instruction encodings and disassembly for 1r instructions. 2012-12-16 17:37:34 +00:00
LLVMBuild.txt Add XCore disassembler. 2012-12-16 17:29:14 +00:00
Makefile Add instruction encodings and disassembly for 1r instructions. 2012-12-16 17:37:34 +00:00
README.txt
XCore.h Pass optLevel to XCoreDAGToDAGISel. 2011-12-15 15:18:35 +00:00
XCore.td Change XCoreAsmPrinter to lower MachineInstrs to MCInsts before emission. 2012-12-16 16:20:48 +00:00
XCoreAsmPrinter.cpp Last in the series of removing unnecessary '0' arguments for 2013-01-09 03:52:05 +00:00
XCoreCallingConv.td
XCoreFrameLowering.cpp Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo 2013-02-21 20:05:00 +00:00
XCoreFrameLowering.h Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo 2013-02-21 20:05:00 +00:00
XCoreInstrFormats.td [XCore] Add missing 2r instructions. 2013-02-17 22:38:05 +00:00
XCoreInstrInfo.cpp Use the new script to sort the includes of every file under lib. 2012-12-03 16:50:05 +00:00
XCoreInstrInfo.h Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 2012-03-17 18:46:09 +00:00
XCoreInstrInfo.td [XCore] Add missing 2r instructions. 2013-02-17 22:38:05 +00:00
XCoreISelDAGToDAG.cpp Fix order of operands for crc8_l4r 2013-01-25 21:20:28 +00:00
XCoreISelLowering.cpp Update TargetLowering ivars for name policy. 2013-02-20 21:13:59 +00:00
XCoreISelLowering.h Fix PR10475 2013-03-01 18:40:30 +00:00
XCoreMachineFunctionInfo.cpp Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreMachineFunctionInfo.h Sort includes for all of the .h files under the 'lib' tree. These were 2012-12-04 07:12:27 +00:00
XCoreMCInstLower.cpp Update comments to match recommended doxygen style. 2012-12-17 12:13:41 +00:00
XCoreMCInstLower.h Update comments to match recommended doxygen style. 2012-12-17 12:13:41 +00:00
XCoreRegisterInfo.cpp Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo 2013-02-21 20:05:00 +00:00
XCoreRegisterInfo.h Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo 2013-02-21 20:05:00 +00:00
XCoreRegisterInfo.td Add instruction encodings and disassembly for 1r instructions. 2012-12-16 17:37:34 +00:00
XCoreSelectionDAGInfo.cpp
XCoreSelectionDAGInfo.h
XCoreSubtarget.cpp Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
XCoreSubtarget.h Sort includes for all of the .h files under the 'lib' tree. These were 2012-12-04 07:12:27 +00:00
XCoreTargetMachine.cpp Switch TargetTransformInfo from an immutable analysis pass that requires 2013-01-07 01:37:14 +00:00
XCoreTargetMachine.h Switch TargetTransformInfo from an immutable analysis pass that requires 2013-01-07 01:37:14 +00:00
XCoreTargetObjectFile.cpp Use the new script to sort the includes of every file under lib. 2012-12-03 16:50:05 +00:00
XCoreTargetObjectFile.h Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00

README.txt 

To-do
-----

* Instruction encodings
* Tailcalls
* Investigate loop alignment
* Add builtins