Karthik Bhat d2ce9392dc Add Support to Recognize and Vectorize NON SIMD instructions in SLPVectorizer. ... This patch adds support to recognize patterns such as fadd,fsub,fadd,fsub.../add,sub,add,sub... and vectorizes them as vector shuffles if they are profitable. These patterns of vector shuffle can later be converted to instructions such as addsubpd etc on X86. Thanks to Arnold and Hal for the reviews. http://reviews.llvm.org/D4015 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211339 91177308-0d34-0410-b5e6-96231b3b80d8		2014-06-20 04:32:48 +00:00
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Hello
InstCombine	Added instruction combine to transform few more negative values addition to subtraction (Part 1)	2014-06-19 10:36:52 +00:00
Instrumentation	[msan] Handle X86 *.psad.* and *.pmadd.* intrinsics.	2014-06-18 12:02:29 +00:00
IPO	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
ObjCARC
Scalar	Updated comments as suggested by Rafael. Thanks.	2014-06-19 14:11:53 +00:00
Utils	Don't build switch lookup tables for dllimport or TLS variables	2014-06-20 00:38:12 +00:00
Vectorize	Add Support to Recognize and Vectorize NON SIMD instructions in SLPVectorizer.	2014-06-20 04:32:48 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile