Vincent Lejeune 98ce62780e R600: Non vector only instruction can be scheduled on trans unit ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514 91177308-0d34-0410-b5e6-96231b3b80d8		2013-07-31 19:31:56 +00:00
..
Analysis
Assembler	Debug Info: enable verifier for testing cases.	2013-07-29 20:18:19 +00:00
Bindings/Ocaml
Bitcode
BugPoint
CodeGen	R600: Non vector only instruction can be scheduled on trans unit	2013-07-31 19:31:56 +00:00
DebugInfo	Move file to X86 and add a triple to fix darwin bots for now.	2013-07-30 00:20:06 +00:00
ExecutionEngine
Feature
FileCheck
Instrumentation	Debug Info: update testing cases to pass verifier.	2013-07-29 18:12:58 +00:00
Integer
JitListener	Debug Info: update testing cases to pass verifier.	2013-07-29 18:12:58 +00:00
Linker
MC	[SystemZ] Add RISBLG and RISBHG instruction definitions	2013-07-31 11:17:35 +00:00
Object	Add support for the 's' operation to llvm-ar.	2013-07-29 12:40:31 +00:00
Other
TableGen
tools
Transforms	Preserve fast-math flags when folding (fsub x, (fneg y)) to (fadd x, y).	2013-07-30 23:53:17 +00:00
Unit
Verifier	Reject bitcasts between address spaces with different sizes	2013-07-31 17:49:08 +00:00
YAMLParser
CMakeLists.txt
lit.cfg
lit.site.cfg.in
Makefile
Makefile.tests
TestRunner.sh