llvm-6502/lib/Target/CellSPU
Kalle Raiskila 2d25d247bd Add branch hinting for SPU.
The implemented algorithm is overly simplistic (just speculate all branches are
taken)- this is work in progress.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126651 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-28 14:08:24 +00:00
..
TargetInfo make -fno-rtti the default unless a directory builds with REQUIRES_RTTI. 2010-01-24 20:43:08 +00:00
CellSDKIntrinsics.td do some serious surgery on CellSPU to get it back into a world 2010-03-15 05:53:47 +00:00
CMakeLists.txt Use explicit add_subdirectory's for LLVM target sublibraries instead 2011-02-20 02:55:27 +00:00
Makefile move all the target's asmprinters into the main target. The piece 2010-11-14 18:43:56 +00:00
README.txt Allow sign-extending of i8 and i16 to i128 on SPU. 2011-01-20 15:49:06 +00:00
SPU64InstrInfo.td Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction. 2010-09-16 12:29:33 +00:00
SPU128InstrInfo.td
SPU.h Add a "nop filler" pass to SPU. 2011-01-11 09:07:54 +00:00
SPU.td
SPUAsmPrinter.cpp Add branch hinting for SPU. 2011-02-28 14:08:24 +00:00
SPUCallingConv.td Remove all traces of v2[i,f]32 on SPU. 2010-08-18 10:04:39 +00:00
SPUFrameLowering.cpp Teach frame lowering to ignore debug values after the terminators. 2011-01-13 21:28:52 +00:00
SPUFrameLowering.h Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. 2011-01-10 12:39:04 +00:00
SPUHazardRecognizers.cpp Various bits of framework needed for precise machine-level selection 2010-12-24 05:03:26 +00:00
SPUHazardRecognizers.h Various bits of framework needed for precise machine-level selection 2010-12-24 05:03:26 +00:00
SPUInstrBuilder.h
SPUInstrFormats.td Add branch hinting for SPU. 2011-02-28 14:08:24 +00:00
SPUInstrInfo.cpp Add branch hinting for SPU. 2011-02-28 14:08:24 +00:00
SPUInstrInfo.h Various bits of framework needed for precise machine-level selection 2010-12-24 05:03:26 +00:00
SPUInstrInfo.td Add branch hinting for SPU. 2011-02-28 14:08:24 +00:00
SPUISelDAGToDAG.cpp Null initialize a few variables flagged by 2011-01-23 17:05:06 +00:00
SPUISelLowering.cpp Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. 2011-02-25 21:41:48 +00:00
SPUISelLowering.h Allow targets to specify a the type of the RHS of a shift parameterized on the type of the LHS. 2011-02-25 21:41:48 +00:00
SPUMachineFunction.h Move per-function state out of TargetLowering subclasses and into 2010-04-17 14:41:14 +00:00
SPUMathInstr.td Remove all traces of v2[i,f]32 on SPU. 2010-08-18 10:04:39 +00:00
SPUMCAsmInfo.cpp Change CodeGen to use .loc directives. This produces a lot more readable output 2010-11-18 02:04:25 +00:00
SPUMCAsmInfo.h Don't pass StringRef by reference. 2010-07-14 22:38:02 +00:00
SPUNodes.td Flag -> Glue, the ongoing saga 2010-12-23 18:28:41 +00:00
SPUNopFiller.cpp Fix a thinko in 123226 that caused test failures on "other" platforms. 2011-01-11 11:27:56 +00:00
SPUOperands.td Don't feed 19 bit immediates to ILA. 2010-12-17 09:36:09 +00:00
SPURegisterInfo.cpp Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. 2011-01-10 12:39:04 +00:00
SPURegisterInfo.h Move more PEI-related hooks to TFI 2010-11-27 23:05:25 +00:00
SPURegisterInfo.td Remove all traces of v2[i,f]32 on SPU. 2010-08-18 10:04:39 +00:00
SPURegisterNames.h
SPUSchedule.td Split up RotateShift itinerary in SPU. 2011-01-17 13:33:19 +00:00
SPUSelectionDAGInfo.cpp Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00
SPUSelectionDAGInfo.h Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00
SPUSubtarget.cpp Enable PostRA scheduling for SPU. 2010-11-29 10:30:25 +00:00
SPUSubtarget.h Enable PostRA scheduling for SPU. 2010-11-29 10:30:25 +00:00
SPUTargetMachine.cpp Add a "nop filler" pass to SPU. 2011-01-11 09:07:54 +00:00
SPUTargetMachine.h Add a "nop filler" pass to SPU. 2011-01-11 09:07:54 +00:00

//===- README.txt - Notes for improving CellSPU-specific code gen ---------===//

This code was contributed by a team from the Computer Systems Research
Department in The Aerospace Corporation:

- Scott Michel (head bottle washer and much of the non-floating point
  instructions)
- Mark Thomas (floating point instructions)
- Michael AuYeung (intrinsics)
- Chandler Carruth (LLVM expertise)
- Nehal Desai (debugging, i32 operations, RoadRunner SPU expertise)

Some minor fixes added by Kalle Raiskila.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, OR
OTHERWISE.  IN NO EVENT SHALL THE AEROSPACE CORPORATION BE LIABLE FOR DAMAGES
OF ANY KIND OR NATURE WHETHER BASED IN CONTRACT, TORT, OR OTHERWISE ARISING
OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE INCLUDING, WITHOUT
LIMITATION, DAMAGES RESULTING FROM LOST OR CONTAMINATED DATA, LOST PROFITS OR
REVENUE, COMPUTER MALFUNCTION, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL,
OR PUNITIVE  DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR
SUCH DAMAGES ARE FORESEEABLE.

---------------------------------------------------------------------------
--WARNING--:
--WARNING--: The CellSPU work is work-in-progress and "alpha" quality code.
--WARNING--:

If you are brave enough to try this code or help to hack on it, be sure
to add 'spu' to configure's --enable-targets option, e.g.:

        ./configure <your_configure_flags_here> \
           --enable-targets=x86,x86_64,powerpc,spu

---------------------------------------------------------------------------

TODO:
* Create a machine pass for performing dual-pipeline scheduling specifically
  for CellSPU, and insert branch prediction instructions as needed.

* i32 instructions:

  * i32 division (work-in-progress)

* i64 support (see i64operations.c test harness):

  * shifts and comparison operators: done
  * sign and zero extension: done
  * addition: done
  * subtraction: needed
  * multiplication: done

* i128 support:

  * zero extension, any extension: done
  * sign extension: done
  * arithmetic operators (add, sub, mul, div): needed
  * logical operations (and, or, shl, srl, sra, xor, nor, nand): needed

    * or: done

* f64 support

  * Comparison operators:
    SETOEQ              unimplemented
    SETOGT              unimplemented
    SETOGE              unimplemented
    SETOLT              unimplemented
    SETOLE              unimplemented
    SETONE              unimplemented
    SETO                done (lowered)
    SETUO               done (lowered)
    SETUEQ              unimplemented
    SETUGT              unimplemented
    SETUGE              unimplemented
    SETULT              unimplemented
    SETULE              unimplemented
    SETUNE              unimplemented

* LLVM vector suport

  * VSETCC needs to be implemented. It's pretty straightforward to code, but
    needs implementation.

* Intrinsics

  * spu.h instrinsics added but not tested. Need to have an operational
    llvm-spu-gcc in order to write a unit test harness.

===-------------------------------------------------------------------------===