Michael Liao 9a508ef64a [PATCH] Fix VGATHER* operand constraints ... Add earlyclobber constaints to prevent input register being allocated as the output register because, according to Intel spec [1], "If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault." --- [1] http://software.intel.com/sites/default/files/319433-014.pdf git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183327 91177308-0d34-0410-b5e6-96231b3b80d8		2013-06-05 18:12:26 +00:00
..
AArch64	Change how we iterate over relocations on ELF.	2013-05-30 03:05:14 +00:00
ARM	Cortex-R5 can issue Thumb2 integer division instructions.	2013-06-04 22:52:09 +00:00
CPP
Generic
Hexagon
Inputs
MBlaze
Mips	[mips] Big-endian code generation for atomic instructions.	2013-05-31 03:25:44 +00:00
MSP430
NVPTX	[NVPTX] Re-enable support for virtual registers in the final output	2013-05-31 12:14:49 +00:00
PowerPC	Change how we iterate over relocations on ELF.	2013-05-30 03:05:14 +00:00
R600	R600: Make sure to schedule AR register uses and defs in the same clause	2013-06-05 03:43:06 +00:00
SI
SPARC	Sparc: Add support for indirect branch and blockaddress in Sparc backend.	2013-06-03 05:58:33 +00:00
SystemZ	[SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses	2013-05-31 13:25:22 +00:00
Thumb
Thumb2	Cortex-R5 can issue Thumb2 integer division instructions.	2013-06-04 22:52:09 +00:00
X86	[PATCH] Fix VGATHER* operand constraints	2013-06-05 18:12:26 +00:00
XCore