Evan Cheng d2ca813549 Correct some load / store instruction itinerary mistakes: ... 1. Cortex-A8 load / store multiplies can only issue on ALU0. 2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues. 3. Correctly model all vld1 and vld2 variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116134 91177308-0d34-0410-b5e6-96231b3b80d8		2010-10-09 01:03:04 +00:00
..
Analysis
Archive
Assembler	The pshufw instruction came about in MMX2 when SSE was introduced. Don't place	2010-10-04 20:24:01 +00:00
Bindings/Ocaml
Bitcode
BugPoint
CodeGen	Correct some load / store instruction itinerary mistakes:	2010-10-09 01:03:04 +00:00
DebugInfo
ExecutionEngine
Feature
FrontendAda
FrontendC
FrontendC++
FrontendFortran
FrontendObjC
FrontendObjC++
Integer
lib
Linker
LLVMC	Generalize tblgen's dag parsing logic to handle arbitrary expressions	2010-10-06 04:55:48 +00:00
MC	Implement a few more binary encoding bits. Still very early stage proof-of-	2010-10-08 21:45:55 +00:00
Other	Remove LoopIndexSplit pass. It is neither maintained nor used by anyone.	2010-10-07 23:29:37 +00:00
Scripts	Fix Formatting.	2010-10-08 03:17:21 +00:00
TableGen	Generalize tblgen's dag parsing logic to handle arbitrary expressions	2010-10-06 04:55:48 +00:00
Transforms	Remove LoopIndexSplit pass. It is neither maintained nor used by anyone.	2010-10-07 23:29:37 +00:00
Unit
Verifier
CMakeLists.txt
lit.cfg
lit.site.cfg.in
Makefile
Makefile.tests
site.exp.in
TestRunner.sh