mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-28 22:29:56 +00:00
1d5a2ad8a6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206609 91177308-0d34-0410-b5e6-96231b3b80d8
335 lines
9.4 KiB
LLVM
335 lines
9.4 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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; arm64 has all tests not involving v1iN.
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define <8 x i8> @shl.v8i8(<8 x i8> %a, <8 x i8> %b) {
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; CHECK-LABEL: shl.v8i8:
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; CHECK: ushl v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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%c = shl <8 x i8> %a, %b
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ret <8 x i8> %c
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}
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define <4 x i16> @shl.v4i16(<4 x i16> %a, <4 x i16> %b) {
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; CHECK-LABEL: shl.v4i16:
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; CHECK: ushl v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
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%c = shl <4 x i16> %a, %b
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ret <4 x i16> %c
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}
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define <2 x i32> @shl.v2i32(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: shl.v2i32:
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; CHECK: ushl v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
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%c = shl <2 x i32> %a, %b
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ret <2 x i32> %c
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}
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define <1 x i64> @shl.v1i64(<1 x i64> %a, <1 x i64> %b) {
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; CHECK-LABEL: shl.v1i64:
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; CHECK: ushl d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%c = shl <1 x i64> %a, %b
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ret <1 x i64> %c
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}
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define <16 x i8> @shl.v16i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: shl.v16i8:
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; CHECK: ushl v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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%c = shl <16 x i8> %a, %b
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ret <16 x i8> %c
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}
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define <8 x i16> @shl.v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: shl.v8i16:
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; CHECK: ushl v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
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%c = shl <8 x i16> %a, %b
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ret <8 x i16> %c
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}
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define <4 x i32> @shl.v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: shl.v4i32:
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; CHECK: ushl v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
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%c = shl <4 x i32> %a, %b
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ret <4 x i32> %c
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}
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define <2 x i64> @shl.v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: shl.v2i64:
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; CHECK: ushl v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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%c = shl <2 x i64> %a, %b
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ret <2 x i64> %c
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}
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define <8 x i8> @lshr.v8i8(<8 x i8> %a, <8 x i8> %b) {
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; CHECK-LABEL: lshr.v8i8:
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; CHECK: neg v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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; CHECK: ushl v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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%c = lshr <8 x i8> %a, %b
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ret <8 x i8> %c
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}
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define <4 x i16> @lshr.v4i16(<4 x i16> %a, <4 x i16> %b) {
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; CHECK-LABEL: lshr.v4i16:
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; CHECK: neg v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
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; CHECK: ushl v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
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%c = lshr <4 x i16> %a, %b
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ret <4 x i16> %c
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}
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define <2 x i32> @lshr.v2i32(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: lshr.v2i32:
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; CHECK: neg v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
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; CHECK: ushl v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
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%c = lshr <2 x i32> %a, %b
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ret <2 x i32> %c
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}
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define <1 x i64> @lshr.v1i64(<1 x i64> %a, <1 x i64> %b) {
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; CHECK-LABEL: lshr.v1i64:
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; CHECK: neg d{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: ushl d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%c = lshr <1 x i64> %a, %b
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ret <1 x i64> %c
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}
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define <16 x i8> @lshr.v16i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: lshr.v16i8:
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; CHECK: neg v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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; CHECK: ushl v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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%c = lshr <16 x i8> %a, %b
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ret <16 x i8> %c
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}
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define <8 x i16> @lshr.v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: lshr.v8i16:
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; CHECK: neg v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
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; CHECK: ushl v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
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%c = lshr <8 x i16> %a, %b
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ret <8 x i16> %c
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}
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define <4 x i32> @lshr.v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: lshr.v4i32:
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; CHECK: neg v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
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; CHECK: ushl v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
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%c = lshr <4 x i32> %a, %b
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ret <4 x i32> %c
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}
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define <2 x i64> @lshr.v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: lshr.v2i64:
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; CHECK: neg v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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; CHECK: ushl v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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%c = lshr <2 x i64> %a, %b
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ret <2 x i64> %c
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}
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define <8 x i8> @ashr.v8i8(<8 x i8> %a, <8 x i8> %b) {
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; CHECK-LABEL: ashr.v8i8:
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; CHECK: neg v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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; CHECK: sshl v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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%c = ashr <8 x i8> %a, %b
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ret <8 x i8> %c
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}
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define <4 x i16> @ashr.v4i16(<4 x i16> %a, <4 x i16> %b) {
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; CHECK-LABEL: ashr.v4i16:
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; CHECK: neg v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
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; CHECK: sshl v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
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%c = ashr <4 x i16> %a, %b
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ret <4 x i16> %c
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}
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define <2 x i32> @ashr.v2i32(<2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: ashr.v2i32:
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; CHECK: neg v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
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; CHECK: sshl v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
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%c = ashr <2 x i32> %a, %b
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ret <2 x i32> %c
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}
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define <1 x i64> @ashr.v1i64(<1 x i64> %a, <1 x i64> %b) {
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; CHECK-LABEL: ashr.v1i64:
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; CHECK: neg d{{[0-9]+}}, d{{[0-9]+}}
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; CHECK: sshl d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}
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%c = ashr <1 x i64> %a, %b
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ret <1 x i64> %c
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}
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define <16 x i8> @ashr.v16i8(<16 x i8> %a, <16 x i8> %b) {
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; CHECK-LABEL: ashr.v16i8:
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; CHECK: neg v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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; CHECK: sshl v{{[0-9]+}}.16b, v{{[0-9]+}}.16b, v{{[0-9]+}}.16b
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%c = ashr <16 x i8> %a, %b
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ret <16 x i8> %c
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}
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define <8 x i16> @ashr.v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: ashr.v8i16:
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; CHECK: neg v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
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; CHECK: sshl v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h
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%c = ashr <8 x i16> %a, %b
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ret <8 x i16> %c
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}
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define <4 x i32> @ashr.v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: ashr.v4i32:
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; CHECK: neg v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
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; CHECK: sshl v{{[0-9]+}}.4s, v{{[0-9]+}}.4s, v{{[0-9]+}}.4s
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%c = ashr <4 x i32> %a, %b
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ret <4 x i32> %c
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}
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define <2 x i64> @ashr.v2i64(<2 x i64> %a, <2 x i64> %b) {
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; CHECK-LABEL: ashr.v2i64:
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; CHECK: neg v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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; CHECK: sshl v{{[0-9]+}}.2d, v{{[0-9]+}}.2d, v{{[0-9]+}}.2d
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%c = ashr <2 x i64> %a, %b
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ret <2 x i64> %c
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}
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define <1 x i64> @shl.v1i64.0(<1 x i64> %a) {
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; CHECK-LABEL: shl.v1i64.0:
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; CHECK-NOT: shl d{{[0-9]+}}, d{{[0-9]+}}, #0
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%c = shl <1 x i64> %a, zeroinitializer
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ret <1 x i64> %c
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}
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define <2 x i32> @shl.v2i32.0(<2 x i32> %a) {
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; CHECK-LABEL: shl.v2i32.0:
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; CHECK-NOT: shl v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, #0
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%c = shl <2 x i32> %a, zeroinitializer
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ret <2 x i32> %c
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}
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; The following test cases test shl/ashr/lshr with v1i8/v1i16/v1i32 types
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define <1 x i8> @shl.v1i8(<1 x i8> %a, <1 x i8> %b) {
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; CHECK-LABEL: shl.v1i8:
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; CHECK: ushl v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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%c = shl <1 x i8> %a, %b
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ret <1 x i8> %c
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}
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define <1 x i16> @shl.v1i16(<1 x i16> %a, <1 x i16> %b) {
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; CHECK-LABEL: shl.v1i16:
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; CHECK: ushl v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
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%c = shl <1 x i16> %a, %b
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ret <1 x i16> %c
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}
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define <1 x i32> @shl.v1i32(<1 x i32> %a, <1 x i32> %b) {
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; CHECK-LABEL: shl.v1i32:
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; CHECK: ushl v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
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%c = shl <1 x i32> %a, %b
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ret <1 x i32> %c
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}
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define <1 x i8> @ashr.v1i8(<1 x i8> %a, <1 x i8> %b) {
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; CHECK-LABEL: ashr.v1i8:
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; CHECK: neg v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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; CHECK: sshl v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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%c = ashr <1 x i8> %a, %b
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ret <1 x i8> %c
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}
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define <1 x i16> @ashr.v1i16(<1 x i16> %a, <1 x i16> %b) {
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; CHECK-LABEL: ashr.v1i16:
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; CHECK: neg v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
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; CHECK: sshl v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
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%c = ashr <1 x i16> %a, %b
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ret <1 x i16> %c
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}
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define <1 x i32> @ashr.v1i32(<1 x i32> %a, <1 x i32> %b) {
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; CHECK-LABEL: ashr.v1i32:
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; CHECK: neg v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
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; CHECK: sshl v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
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%c = ashr <1 x i32> %a, %b
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ret <1 x i32> %c
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}
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define <1 x i8> @lshr.v1i8(<1 x i8> %a, <1 x i8> %b) {
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; CHECK-LABEL: lshr.v1i8:
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; CHECK: neg v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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; CHECK: ushl v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, v{{[0-9]+}}.8b
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%c = lshr <1 x i8> %a, %b
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ret <1 x i8> %c
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}
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define <1 x i16> @lshr.v1i16(<1 x i16> %a, <1 x i16> %b) {
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; CHECK-LABEL: lshr.v1i16:
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; CHECK: neg v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
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; CHECK: ushl v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h
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%c = lshr <1 x i16> %a, %b
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ret <1 x i16> %c
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}
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define <1 x i32> @lshr.v1i32(<1 x i32> %a, <1 x i32> %b) {
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; CHECK-LABEL: lshr.v1i32:
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; CHECK: neg v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
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; CHECK: ushl v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, v{{[0-9]+}}.2s
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%c = lshr <1 x i32> %a, %b
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ret <1 x i32> %c
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}
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define <1 x i8> @shl.v1i8.imm(<1 x i8> %a) {
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; CHECK-LABEL: shl.v1i8.imm:
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; CHECK: shl v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, #3
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%c = shl <1 x i8> %a, <i8 3>
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ret <1 x i8> %c
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}
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define <1 x i16> @shl.v1i16.imm(<1 x i16> %a) {
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; CHECK-LABEL: shl.v1i16.imm:
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; CHECK: shl v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, #5
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%c = shl <1 x i16> %a, <i16 5>
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ret <1 x i16> %c
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}
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define <1 x i32> @shl.v1i32.imm(<1 x i32> %a) {
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; CHECK-LABEL: shl.v1i32.imm:
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; CHECK-NOT: shl v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, #0
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%c = shl <1 x i32> %a, zeroinitializer
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ret <1 x i32> %c
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}
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define <1 x i8> @ashr.v1i8.imm(<1 x i8> %a) {
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; CHECK-LABEL: ashr.v1i8.imm:
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; CHECK: sshr v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, #3
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%c = ashr <1 x i8> %a, <i8 3>
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ret <1 x i8> %c
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}
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define <1 x i16> @ashr.v1i16.imm(<1 x i16> %a) {
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; CHECK-LABEL: ashr.v1i16.imm:
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; CHECK: sshr v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, #10
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%c = ashr <1 x i16> %a, <i16 10>
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ret <1 x i16> %c
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}
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define <1 x i32> @ashr.v1i32.imm(<1 x i32> %a) {
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; CHECK-LABEL: ashr.v1i32.imm:
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; CHECK: sshr v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, #31
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%c = ashr <1 x i32> %a, <i32 31>
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ret <1 x i32> %c
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}
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define <1 x i8> @lshr.v1i8.imm(<1 x i8> %a) {
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; CHECK-LABEL: lshr.v1i8.imm:
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; CHECK: ushr v{{[0-9]+}}.8b, v{{[0-9]+}}.8b, #3
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%c = lshr <1 x i8> %a, <i8 3>
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ret <1 x i8> %c
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}
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define <1 x i16> @lshr.v1i16.imm(<1 x i16> %a) {
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; CHECK-LABEL: lshr.v1i16.imm:
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; CHECK: ushr v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, #10
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%c = lshr <1 x i16> %a, <i16 10>
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ret <1 x i16> %c
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}
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define <1 x i32> @lshr.v1i32.imm(<1 x i32> %a) {
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; CHECK-LABEL: lshr.v1i32.imm:
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; CHECK: ushr v{{[0-9]+}}.2s, v{{[0-9]+}}.2s, #31
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%c = lshr <1 x i32> %a, <i32 31>
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ret <1 x i32> %c
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}
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