Sanjay Patel 9b4cc76745 Merge consecutive 16-byte loads into one 32-byte load (PR22329) ... This patch detects consecutive vector loads using the existing EltsFromConsecutiveLoads() logic. This fixes: http://llvm.org/bugs/show_bug.cgi?id=22329 This patch effectively reverts the tablegen additions of D6492 / http://reviews.llvm.org/rL224344 ...which in hindsight were a horrible hack. The test cases that were added with that patch are simply modified to load from varying offsets of a base pointer. These loads did not match the existing tablegen patterns. A happy side effect of doing this optimization earlier is that we can now fold the load into a math op where possible; this is shown in some of the updated checks in the test file. Differential Revision: http://reviews.llvm.org/D7303 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228006 91177308-0d34-0410-b5e6-96231b3b80d8		2015-02-03 18:54:00 +00:00
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AArch64	[AArch64] Prefer DUP/MOV ("CPY") to INS for vector_extract.	2015-02-02 17:55:57 +00:00
ARM	Fix ARM peephole optimizeCompare to avoid optimizing unsigned cmp to 0.	2015-02-02 16:56:50 +00:00
BPF	bpf: add missing lit.local.cfg	2015-01-24 18:20:52 +00:00
CPP
Generic	overloaded-intrinsic-name: exercise anyptr on struct	2015-01-27 20:03:08 +00:00
Hexagon	[Hexagon] Converting complex number intrinsics and adding tests.	2015-02-03 18:16:28 +00:00
Inputs
Mips	Move the Mips target to storing the ABI in the TargetMachine rather	2015-01-26 17:33:46 +00:00
MSP430
NVPTX	[NVPTX] Emit .pragma "nounroll" for loops marked with nounroll	2015-02-01 02:27:45 +00:00
PowerPC	Disable 32-bit tests in tls-pic.ll until they can be repaired	2015-02-03 16:57:38 +00:00
R600	R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VI	2015-02-03 17:38:12 +00:00
SPARC	Use the integrated assembler by default on SPARC.	2015-01-14 07:53:39 +00:00
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X86	Merge consecutive 16-byte loads into one 32-byte load (PR22329)	2015-02-03 18:54:00 +00:00
XCore