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Each SM and PTX version is modeled as a subtarget feature/CPU. Additionally, PTX 3.1 is added as the default PTX version to be out-of-the-box compatible with CUDA 5.0. Available CPUs for this target: sm_10 - Select the sm_10 processor. sm_11 - Select the sm_11 processor. sm_12 - Select the sm_12 processor. sm_13 - Select the sm_13 processor. sm_20 - Select the sm_20 processor. sm_21 - Select the sm_21 processor. sm_30 - Select the sm_30 processor. sm_35 - Select the sm_35 processor. Available features for this target: ptx30 - Use PTX version 3.0. ptx31 - Use PTX version 3.1. sm_10 - Target SM 1.0. sm_11 - Target SM 1.1. sm_12 - Target SM 1.2. sm_13 - Target SM 1.3. sm_20 - Target SM 2.0. sm_21 - Target SM 2.1. sm_30 - Target SM 3.0. sm_35 - Target SM 3.5. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167699 91177308-0d34-0410-b5e6-96231b3b80d8
75 lines
2.8 KiB
TableGen
75 lines
2.8 KiB
TableGen
//===- NVPTX.td - Describe the NVPTX Target Machine -----------*- tblgen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This is the top level entry point for the NVPTX target.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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include "NVPTXRegisterInfo.td"
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include "NVPTXInstrInfo.td"
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//===----------------------------------------------------------------------===//
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// Subtarget Features.
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// - We use the SM version number instead of explicit feature table.
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// - Need at least one feature to avoid generating zero sized array by
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// TableGen in NVPTXGenSubtarget.inc.
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//===----------------------------------------------------------------------===//
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// SM Versions
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def SM10 : SubtargetFeature<"sm_10", "SmVersion", "10",
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"Target SM 1.0">;
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def SM11 : SubtargetFeature<"sm_11", "SmVersion", "11",
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"Target SM 1.1">;
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def SM12 : SubtargetFeature<"sm_12", "SmVersion", "12",
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"Target SM 1.2">;
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def SM13 : SubtargetFeature<"sm_13", "SmVersion", "13",
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"Target SM 1.3">;
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def SM20 : SubtargetFeature<"sm_20", "SmVersion", "20",
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"Target SM 2.0">;
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def SM21 : SubtargetFeature<"sm_21", "SmVersion", "21",
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"Target SM 2.1">;
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def SM30 : SubtargetFeature<"sm_30", "SmVersion", "30",
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"Target SM 3.0">;
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def SM35 : SubtargetFeature<"sm_35", "SmVersion", "35",
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"Target SM 3.5">;
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// PTX Versions
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def PTX30 : SubtargetFeature<"ptx30", "PTXVersion", "30",
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"Use PTX version 3.0">;
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def PTX31 : SubtargetFeature<"ptx31", "PTXVersion", "31",
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"Use PTX version 3.1">;
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//===----------------------------------------------------------------------===//
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// NVPTX supported processors.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"sm_10", [SM10]>;
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def : Proc<"sm_11", [SM11]>;
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def : Proc<"sm_12", [SM12]>;
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def : Proc<"sm_13", [SM13]>;
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def : Proc<"sm_20", [SM20]>;
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def : Proc<"sm_21", [SM21]>;
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def : Proc<"sm_30", [SM30]>;
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def : Proc<"sm_35", [SM35]>;
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def NVPTXInstrInfo : InstrInfo {
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}
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def NVPTX : Target {
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let InstructionSet = NVPTXInstrInfo;
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}
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