llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-10 17:07:06 +00:00

History

Jakob Stoklund Olesen 600f171486 RISC architectures get their memory operand folding for free. The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8		2010-07-11 19:19:13 +00:00
..
AsmPrinter
TargetInfo
Alpha.h
Alpha.td
AlphaBranchSelector.cpp
AlphaCallingConv.td
AlphaCodeEmitter.cpp
AlphaInstrFormats.td	Remove isTwoAddress from Alpha.	2010-06-21 18:48:55 +00:00
AlphaInstrInfo.cpp	RISC architectures get their memory operand folding for free.	2010-07-11 19:19:13 +00:00
AlphaInstrInfo.h	RISC architectures get their memory operand folding for free.	2010-07-11 19:19:13 +00:00
AlphaInstrInfo.td	Remove isTwoAddress from Alpha.	2010-06-21 18:48:55 +00:00
AlphaISelDAGToDAG.cpp
AlphaISelLowering.cpp	Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake.	2010-07-07 22:15:37 +00:00
AlphaISelLowering.h	Split the SDValue out of OutputArg so that SelectionDAG-independent	2010-07-07 15:54:55 +00:00
AlphaJITInfo.cpp
AlphaJITInfo.h
AlphaLLRP.cpp
AlphaMachineFunctionInfo.h
AlphaMCAsmInfo.cpp
AlphaMCAsmInfo.h
AlphaRegisterInfo.cpp	cleanup	2010-06-02 13:53:17 +00:00
AlphaRegisterInfo.h	cleanup	2010-06-02 13:53:17 +00:00
AlphaRegisterInfo.td
AlphaRelocations.h
AlphaSchedule.td
AlphaSelectionDAGInfo.cpp
AlphaSelectionDAGInfo.h
AlphaSubtarget.cpp
AlphaSubtarget.h
AlphaTargetMachine.cpp
AlphaTargetMachine.h
CMakeLists.txt
Makefile
README.txt

README.txt

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum accross bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extentions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html