mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-26 06:29:20 +00:00
9d928c223f
scavenger gets confused about register liveness if it doesn't see them. I'm not thrilled with this solution, but it only comes up when there are dead copies in the code, which is something that hopefully doesn't happen much. Here is what happens in pr4100: As shown in the following excerpt from the debug output of llc, the source of a move gets reloaded from the stack, inserting a new load instruction before the move. Since that source operand is a kill, the physical register is free to be reused for the destination of the move. The move ends up being a no-op, copying R3 to R3, so it is deleted. But, it leaves behind the load to reload %reg1028 into R3, and that load is not updated to show that it's destination operand (R3) is dead. The scavenger gets confused by that load because it thinks that R3 is live. Starting RegAlloc of: %reg1025<def,dead> = MOVr %reg1028<kill>, 14, %reg0, %reg0 Regs have values: Reloading %reg1028 into R3 Last use of R3[%reg1028], removing it from live set Assigning R3 to %reg1025 Register R3 [%reg1025] is never used, removing it from live set Alternative solutions might be either marking the load as dead, or zapping the load along with the no-op copy. I couldn't see an easy way to do either of those, though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71196 91177308-0d34-0410-b5e6-96231b3b80d8 |
||
---|---|---|
.. | ||
AsmPrinter | ||
SelectionDAG | ||
BranchFolding.cpp | ||
CMakeLists.txt | ||
CodePlacementOpt.cpp | ||
DeadMachineInstructionElim.cpp | ||
ELFWriter.cpp | ||
ELFWriter.h | ||
GCMetadata.cpp | ||
GCMetadataPrinter.cpp | ||
GCStrategy.cpp | ||
IfConversion.cpp | ||
IntrinsicLowering.cpp | ||
LatencyPriorityQueue.cpp | ||
LiveInterval.cpp | ||
LiveIntervalAnalysis.cpp | ||
LiveStackAnalysis.cpp | ||
LiveVariables.cpp | ||
LLVMTargetMachine.cpp | ||
LowerSubregs.cpp | ||
MachineBasicBlock.cpp | ||
MachineDominators.cpp | ||
MachineFunction.cpp | ||
MachineInstr.cpp | ||
MachineLICM.cpp | ||
MachineLoopInfo.cpp | ||
MachineModuleInfo.cpp | ||
MachinePassRegistry.cpp | ||
MachineRegisterInfo.cpp | ||
MachineSink.cpp | ||
MachOWriter.cpp | ||
MachOWriter.h | ||
Makefile | ||
OcamlGC.cpp | ||
Passes.cpp | ||
PBQP.cpp | ||
PBQP.h | ||
PHIElimination.cpp | ||
PostRASchedulerList.cpp | ||
PreAllocSplitting.cpp | ||
PrologEpilogInserter.cpp | ||
PseudoSourceValue.cpp | ||
README.txt | ||
RegAllocBigBlock.cpp | ||
RegAllocLinearScan.cpp | ||
RegAllocLocal.cpp | ||
RegAllocPBQP.cpp | ||
RegAllocSimple.cpp | ||
RegisterCoalescer.cpp | ||
RegisterScavenging.cpp | ||
ScheduleDAG.cpp | ||
ScheduleDAGEmit.cpp | ||
ScheduleDAGInstrs.cpp | ||
ScheduleDAGInstrs.h | ||
ScheduleDAGPrinter.cpp | ||
ShadowStackGC.cpp | ||
SimpleRegisterCoalescing.cpp | ||
SimpleRegisterCoalescing.h | ||
StackProtector.cpp | ||
StackSlotColoring.cpp | ||
StrongPHIElimination.cpp | ||
TargetInstrInfoImpl.cpp | ||
TwoAddressInstructionPass.cpp | ||
UnreachableBlockElim.cpp | ||
VirtRegMap.cpp | ||
VirtRegMap.h | ||
VirtRegRewriter.cpp | ||
VirtRegRewriter.h |
//===---------------------------------------------------------------------===// Common register allocation / spilling problem: mul lr, r4, lr str lr, [sp, #+52] ldr lr, [r1, #+32] sxth r3, r3 ldr r4, [sp, #+52] mla r4, r3, lr, r4 can be: mul lr, r4, lr mov r4, lr str lr, [sp, #+52] ldr lr, [r1, #+32] sxth r3, r3 mla r4, r3, lr, r4 and then "merge" mul and mov: mul r4, r4, lr str lr, [sp, #+52] ldr lr, [r1, #+32] sxth r3, r3 mla r4, r3, lr, r4 It also increase the likelyhood the store may become dead. //===---------------------------------------------------------------------===// I think we should have a "hasSideEffects" flag (which is automatically set for stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able to remat any instruction that has no side effects, if it can handle it and if profitable. For now, I'd suggest having the remat stuff work like this: 1. I need to spill/reload this thing. 2. Check to see if it has side effects. 3. Check to see if it is simple enough: e.g. it only has one register destination and no register input. 4. If so, clone the instruction, do the xform, etc. Advantages of this are: 1. the .td file describes the behavior of the instructions, not the way the algorithm should work. 2. as remat gets smarter in the future, we shouldn't have to be changing the .td files. 3. it is easier to explain what the flag means in the .td file, because you don't have to pull in the explanation of how the current remat algo works. Some potential added complexities: 1. Some instructions have to be glued to it's predecessor or successor. All of the PC relative instructions and condition code setting instruction. We could mark them as hasSideEffects, but that's not quite right. PC relative loads from constantpools can be remat'ed, for example. But it requires more than just cloning the instruction. Some instructions can be remat'ed but it expands to more than one instruction. But allocator will have to make a decision. 4. As stated in 3, not as simple as cloning in some cases. The target will have to decide how to remat it. For example, an ARM 2-piece constant generation instruction is remat'ed as a load from constantpool. //===---------------------------------------------------------------------===// bb27 ... ... %reg1037 = ADDri %reg1039, 1 %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10 Successors according to CFG: 0x8b03bf0 (#5) bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5): Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4) %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0> Note ADDri is not a two-address instruction. However, its result %reg1037 is an operand of the PHI node in bb76 and its operand %reg1039 is the result of the PHI node. We should treat it as a two-address code and make sure the ADDri is scheduled after any node that reads %reg1039. //===---------------------------------------------------------------------===// Use local info (i.e. register scavenger) to assign it a free register to allow reuse: ldr r3, [sp, #+4] add r3, r3, #3 ldr r2, [sp, #+8] add r2, r2, #2 ldr r1, [sp, #+4] <== add r1, r1, #1 ldr r0, [sp, #+4] add r0, r0, #2 //===---------------------------------------------------------------------===// LLVM aggressively lift CSE out of loop. Sometimes this can be negative side- effects: R1 = X + 4 R2 = X + 7 R3 = X + 15 loop: load [i + R1] ... load [i + R2] ... load [i + R3] Suppose there is high register pressure, R1, R2, R3, can be spilled. We need to implement proper re-materialization to handle this: R1 = X + 4 R2 = X + 7 R3 = X + 15 loop: R1 = X + 4 @ re-materialized load [i + R1] ... R2 = X + 7 @ re-materialized load [i + R2] ... R3 = X + 15 @ re-materialized load [i + R3] Furthermore, with re-association, we can enable sharing: R1 = X + 4 R2 = X + 7 R3 = X + 15 loop: T = i + X load [T + 4] ... load [T + 7] ... load [T + 15] //===---------------------------------------------------------------------===// It's not always a good idea to choose rematerialization over spilling. If all the load / store instructions would be folded then spilling is cheaper because it won't require new live intervals / registers. See 2003-05-31-LongShifts for an example. //===---------------------------------------------------------------------===// With a copying garbage collector, derived pointers must not be retained across collector safe points; the collector could move the objects and invalidate the derived pointer. This is bad enough in the first place, but safe points can crop up unpredictably. Consider: %array = load { i32, [0 x %obj] }** %array_addr %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n %old = load %obj** %nth_el %z = div i64 %x, %y store %obj* %new, %obj** %nth_el If the i64 division is lowered to a libcall, then a safe point will (must) appear for the call site. If a collection occurs, %array and %nth_el no longer point into the correct object. The fix for this is to copy address calculations so that dependent pointers are never live across safe point boundaries. But the loads cannot be copied like this if there was an intervening store, so may be hard to get right. Only a concurrent mutator can trigger a collection at the libcall safe point. So single-threaded programs do not have this requirement, even with a copying collector. Still, LLVM optimizations would probably undo a front-end's careful work. //===---------------------------------------------------------------------===// The ocaml frametable structure supports liveness information. It would be good to support it. //===---------------------------------------------------------------------===// The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be revisited. The check is there to work around a misuse of directives in inline assembly. //===---------------------------------------------------------------------===// It would be good to detect collector/target compatibility instead of silently doing the wrong thing. //===---------------------------------------------------------------------===// It would be really nice to be able to write patterns in .td files for copies, which would eliminate a bunch of explicit predicates on them (e.g. no side effects). Once this is in place, it would be even better to have tblgen synthesize the various copy insertion/inspection methods in TargetInstrInfo. //===---------------------------------------------------------------------===// Stack coloring improvments: 1. Do proper LiveStackAnalysis on all stack objects including those which are not spill slots. 2. Reorder objects to fill in gaps between objects. e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4