llvm-6502/lib/Target/ARM/MCTargetDesc
Jim Grosbach 9da7892fbe ARM: Thumb ldr(literal) base address alignment is 32-bits.
The base address for the PC-relative load is Align(PC,4), so it's the
address of the word containing the 16-bit instruction, not the address
of the instruction itself. Ugh.

rdar://11314619

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155659 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-26 20:48:12 +00:00
..
ARMAddressingModes.h
ARMAsmBackend.cpp ARM: Thumb ldr(literal) base address alignment is 32-bits. 2012-04-26 20:48:12 +00:00
ARMBaseInfo.h
ARMELFObjectWriter.cpp
ARMFixupKinds.h
ARMMachObjectWriter.cpp
ARMMCAsmInfo.cpp
ARMMCAsmInfo.h
ARMMCCodeEmitter.cpp Unify internal representation of ARM instructions with a register right-shifted by #32. These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation. 2012-04-25 18:00:18 +00:00
ARMMCExpr.cpp
ARMMCExpr.h
ARMMCTargetDesc.cpp If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assume 2012-04-26 01:13:36 +00:00
ARMMCTargetDesc.h If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assume 2012-04-26 01:13:36 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile