Ahmed Bougacha 7fac1d945f [SelectionDAG] Allow targets to specify legality of extloads' result ... type (in addition to the memory type). The *LoadExt* legalization handling used to only have one type, the memory type. This forced users to assume that as long as the extload for the memory type was declared legal, and the result type was legal, the whole extload was legal. However, this isn't always the case. For instance, on X86, with AVX, this is legal: v4i32 load, zext from v4i8 but this isn't: v4i64 load, zext from v4i8 Whereas v4i64 is (arguably) legal, even without AVX2. Note that the same thing was done a while ago for truncstores (r46140), but I assume no one needed it yet for extloads, so here we go. Calls to getLoadExtAction were changed to add the value type, found manually in the surrounding code. Calls to setLoadExtAction were mechanically changed, by wrapping the call in a loop, to match previous behavior. The loop iterates over the MVT subrange corresponding to the memory type (FP vectors, etc...). I also pulled neighboring setTruncStoreActions into some of the loops; those shouldn't make a difference, as the additional types are illegal. (e.g., i128->i1 truncstores on PPC.) No functional change intended. Differential Revision: http://reviews.llvm.org/D6532 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225421 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-08 00:51:32 +00:00
..
Disassembler
MCTargetDesc	Reverting 225045 and 225043 and XFAIL multiline.ll on hexagon	2014-12-31 17:14:35 +00:00
TargetInfo
CMakeLists.txt
Hexagon.h
Hexagon.td	[Hexagon] Adding dealloc_return encoding and absolute address stores.	2015-01-06 16:15:15 +00:00
HexagonAsmPrinter.cpp
HexagonAsmPrinter.h
HexagonCallingConv.td
HexagonCallingConvLower.cpp
HexagonCallingConvLower.h
HexagonCFGOptimizer.cpp
HexagonCopyToCombine.cpp	[Hexagon] Dropping old combine instructions without encodings.	2014-12-30 17:53:54 +00:00
HexagonExpandPredSpillCode.cpp	[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests.	2014-12-29 20:44:51 +00:00
HexagonFixupHwLoops.cpp
HexagonFrameLowering.cpp	[Hexagon] Adding dealloc_return encoding and absolute address stores.	2015-01-06 16:15:15 +00:00
HexagonFrameLowering.h
HexagonHardwareLoops.cpp
HexagonInstrFormats.td
HexagonInstrFormatsV4.td	[Hexagon] Adding compound jump encodings.	2015-01-06 20:03:31 +00:00
HexagonInstrInfo.cpp	[Hexagon] Adding dealloc_return encoding and absolute address stores.	2015-01-06 16:15:15 +00:00
HexagonInstrInfo.h
HexagonInstrInfo.td	[Hexagon] Adding round reg/imm and bitsplit instructions.	2015-01-05 18:08:21 +00:00
HexagonInstrInfoV3.td
HexagonInstrInfoV4.td	[Hexagon] Adding compound jump encodings.	2015-01-06 20:03:31 +00:00
HexagonInstrInfoV5.td	[Hexagon] Fix 225372 USR register is not fully complete. Removing Uses = [USR] maintains existing functionality to old instructions without encodings.	2015-01-07 20:43:38 +00:00
HexagonIntrinsics.td
HexagonIntrinsicsDerived.td
HexagonIntrinsicsV3.td
HexagonIntrinsicsV4.td
HexagonIntrinsicsV5.td
HexagonISelDAGToDAG.cpp	[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests.	2014-12-29 20:44:51 +00:00
HexagonISelLowering.cpp	[SelectionDAG] Allow targets to specify legality of extloads' result	2015-01-08 00:51:32 +00:00
HexagonISelLowering.h	[Hexagon] Adding encoding for popcount, fastcorner, dword asr with rounding.	2015-01-07 20:07:28 +00:00
HexagonMachineFunctionInfo.cpp
HexagonMachineFunctionInfo.h
HexagonMachineScheduler.cpp
HexagonMachineScheduler.h
HexagonMCInstLower.cpp
HexagonNewValueJump.cpp
HexagonOperands.td	[Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dcfetch.	2015-01-06 19:03:20 +00:00
HexagonPeephole.cpp	[Hexagon] Dropping old combine instructions without encodings.	2014-12-30 17:53:54 +00:00
HexagonRegisterInfo.cpp	[Hexagon] Adding post-increment register form stores and register-immediate form stores with tests.	2014-12-29 20:44:51 +00:00
HexagonRegisterInfo.h
HexagonRegisterInfo.td
HexagonRemoveSZExtArgs.cpp
HexagonSchedule.td
HexagonScheduleV4.td
HexagonSelectCCInfo.td
HexagonSelectionDAGInfo.cpp
HexagonSelectionDAGInfo.h
HexagonSplitConst32AndConst64.cpp
HexagonSplitTFRCondSets.cpp
HexagonSubtarget.cpp
HexagonSubtarget.h
HexagonTargetMachine.cpp
HexagonTargetMachine.h
HexagonTargetObjectFile.cpp
HexagonTargetObjectFile.h
HexagonVarargsCallingConvention.h
HexagonVLIWPacketizer.cpp	[Hexagon] Updating constant extender def, adding alu-not instructions, compare to general register, and inverted compares.	2014-12-30 15:44:17 +00:00
LLVMBuild.txt
Makefile