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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226596 91177308-0d34-0410-b5e6-96231b3b80d8
209 lines
7.5 KiB
C++
209 lines
7.5 KiB
C++
//===-- SIPrepareScratchRegs.cpp - Use predicates for control flow --------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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///
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/// This pass loads scratch pointer and scratch offset into a register or a
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/// frame index which can be used anywhere in the program. These values will
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/// be used for spilling VGPRs.
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///
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "SIDefines.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/LLVMContext.h"
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using namespace llvm;
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namespace {
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class SIPrepareScratchRegs : public MachineFunctionPass {
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private:
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static char ID;
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public:
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SIPrepareScratchRegs() : MachineFunctionPass(ID) { }
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bool runOnMachineFunction(MachineFunction &MF) override;
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const char *getPassName() const override {
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return "SI prepare scratch registers";
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}
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};
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} // End anonymous namespace
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char SIPrepareScratchRegs::ID = 0;
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FunctionPass *llvm::createSIPrepareScratchRegs() {
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return new SIPrepareScratchRegs();
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}
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bool SIPrepareScratchRegs::runOnMachineFunction(MachineFunction &MF) {
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SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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const SIInstrInfo *TII =
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static_cast<const SIInstrInfo *>(MF.getSubtarget().getInstrInfo());
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const SIRegisterInfo *TRI = &TII->getRegisterInfo();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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MachineFrameInfo *FrameInfo = MF.getFrameInfo();
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MachineBasicBlock *Entry = MF.begin();
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MachineBasicBlock::iterator I = Entry->begin();
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DebugLoc DL = I->getDebugLoc();
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// FIXME: If we don't have enough VGPRs for SGPR spilling we will need to
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// run this pass.
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if (!MFI->hasSpilledVGPRs())
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return false;
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unsigned ScratchPtrPreloadReg =
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TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_PTR);
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unsigned ScratchOffsetPreloadReg =
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TRI->getPreloadedValue(MF, SIRegisterInfo::SCRATCH_WAVE_OFFSET);
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if (!Entry->isLiveIn(ScratchPtrPreloadReg))
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Entry->addLiveIn(ScratchPtrPreloadReg);
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if (!Entry->isLiveIn(ScratchOffsetPreloadReg))
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Entry->addLiveIn(ScratchOffsetPreloadReg);
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// Load the scratch offset.
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unsigned ScratchOffsetReg =
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TRI->findUnusedRegister(MRI, &AMDGPU::SGPR_32RegClass);
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int ScratchOffsetFI = -1;
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if (ScratchOffsetReg != AMDGPU::NoRegister) {
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// Found an SGPR to use
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MRI.setPhysRegUsed(ScratchOffsetReg);
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BuildMI(*Entry, I, DL, TII->get(AMDGPU::S_MOV_B32), ScratchOffsetReg)
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.addReg(ScratchOffsetPreloadReg);
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} else {
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// No SGPR is available, we must spill.
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ScratchOffsetFI = FrameInfo->CreateSpillStackObject(4,4);
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BuildMI(*Entry, I, DL, TII->get(AMDGPU::SI_SPILL_S32_SAVE))
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.addReg(ScratchOffsetPreloadReg)
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.addFrameIndex(ScratchOffsetFI)
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.addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
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.addReg(AMDGPU::SGPR0, RegState::Undef);
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}
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// Now that we have the scratch pointer and offset values, we need to
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// add them to all the SI_SPILL_V* instructions.
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RegScavenger RS;
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unsigned ScratchRsrcFI = FrameInfo->CreateSpillStackObject(16, 4);
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RS.addScavengingFrameIndex(ScratchRsrcFI);
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for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
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BI != BE; ++BI) {
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MachineBasicBlock &MBB = *BI;
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// Add the scratch offset reg as a live-in so that the register scavenger
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// doesn't re-use it.
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if (!MBB.isLiveIn(ScratchOffsetReg) &&
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ScratchOffsetReg != AMDGPU::NoRegister)
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MBB.addLiveIn(ScratchOffsetReg);
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RS.enterBasicBlock(&MBB);
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
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I != E; ++I) {
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MachineInstr &MI = *I;
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RS.forward(I);
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DebugLoc DL = MI.getDebugLoc();
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switch(MI.getOpcode()) {
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default: break;
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case AMDGPU::SI_SPILL_V512_SAVE:
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case AMDGPU::SI_SPILL_V256_SAVE:
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case AMDGPU::SI_SPILL_V128_SAVE:
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case AMDGPU::SI_SPILL_V96_SAVE:
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case AMDGPU::SI_SPILL_V64_SAVE:
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case AMDGPU::SI_SPILL_V32_SAVE:
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case AMDGPU::SI_SPILL_V32_RESTORE:
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case AMDGPU::SI_SPILL_V64_RESTORE:
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case AMDGPU::SI_SPILL_V128_RESTORE:
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case AMDGPU::SI_SPILL_V256_RESTORE:
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case AMDGPU::SI_SPILL_V512_RESTORE:
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// Scratch resource
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unsigned ScratchRsrcReg =
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RS.scavengeRegister(&AMDGPU::SReg_128RegClass, 0);
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uint64_t Rsrc = AMDGPU::RSRC_DATA_FORMAT | AMDGPU::RSRC_TID_ENABLE |
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0xffffffff; // Size
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unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
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unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
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unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
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unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
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BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc0)
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.addExternalSymbol("SCRATCH_RSRC_DWORD0")
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.addReg(ScratchRsrcReg, RegState::ImplicitDefine);
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BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc1)
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.addExternalSymbol("SCRATCH_RSRC_DWORD1")
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.addReg(ScratchRsrcReg, RegState::ImplicitDefine);
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BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc2)
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.addImm(Rsrc & 0xffffffff)
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.addReg(ScratchRsrcReg, RegState::ImplicitDefine);
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BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), Rsrc3)
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.addImm(Rsrc >> 32)
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.addReg(ScratchRsrcReg, RegState::ImplicitDefine);
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// Scratch Offset
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if (ScratchOffsetReg == AMDGPU::NoRegister) {
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ScratchOffsetReg = RS.scavengeRegister(&AMDGPU::SGPR_32RegClass, 0);
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BuildMI(MBB, I, DL, TII->get(AMDGPU::SI_SPILL_S32_RESTORE),
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ScratchOffsetReg)
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.addFrameIndex(ScratchOffsetFI)
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.addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef)
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.addReg(AMDGPU::SGPR0, RegState::Undef);
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} else if (!MBB.isLiveIn(ScratchOffsetReg)) {
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MBB.addLiveIn(ScratchOffsetReg);
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}
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if (ScratchRsrcReg == AMDGPU::NoRegister ||
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ScratchOffsetReg == AMDGPU::NoRegister) {
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LLVMContext &Ctx = MF.getFunction()->getContext();
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Ctx.emitError("ran out of SGPRs for spilling VGPRs");
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ScratchRsrcReg = AMDGPU::SGPR0;
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ScratchOffsetReg = AMDGPU::SGPR0;
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}
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MI.getOperand(2).setReg(ScratchRsrcReg);
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MI.getOperand(2).setIsKill(true);
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MI.getOperand(2).setIsUndef(false);
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MI.getOperand(3).setReg(ScratchOffsetReg);
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MI.getOperand(3).setIsUndef(false);
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MI.getOperand(3).setIsKill(false);
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MI.addOperand(MachineOperand::CreateReg(Rsrc0, false, true, true));
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MI.addOperand(MachineOperand::CreateReg(Rsrc1, false, true, true));
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MI.addOperand(MachineOperand::CreateReg(Rsrc2, false, true, true));
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MI.addOperand(MachineOperand::CreateReg(Rsrc3, false, true, true));
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break;
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}
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}
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}
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return true;
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}
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