mirror of
https://github.com/c64scene-ar/llvm-6502.git
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23a72c8f7e
This adds support for the last missing construct to parse TLS-related assembler code: add 3, 4, symbol@tls The ADD8TLS currently hard-codes the @tls into the assembler string. This cannot be handled by the asm parser, since @tls is parsed as a symbol variant. This patch changes ADD8TLS to have the @tls suffix printed as symbol variant on output too, which allows us to remove the isCodeGenOnly marker from ADD8TLS. This in turn means that we can add a AsmOperand to accept @tls marked symbols on input. As a side effect, this means that the fixup_ppc_tlsreg fixup type is no longer necessary and can be merged into fixup_ppc_nofixup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185692 91177308-0d34-0410-b5e6-96231b3b80d8
99 lines
2.4 KiB
ArmAsm
99 lines
2.4 KiB
ArmAsm
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# RUN: not llvm-mc -triple powerpc64-unknown-unknown < %s 2> %t
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# RUN: FileCheck < %t %s
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# Register operands
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: add 32, 32, 32
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add 32, 32, 32
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# CHECK: error: invalid register name
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# CHECK-NEXT: add %r32, %r32, %r32
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add %r32, %r32, %r32
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# TLS register operands
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: add 3, symbol@tls, 4
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add 3, symbol@tls, 4
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: subf 3, 4, symbol@tls
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subf 3, 4, symbol@tls
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# Signed 16-bit immediate operands
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: addi 1, 0, -32769
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addi 1, 0, -32769
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: addi 1, 0, 32768
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addi 1, 0, 32768
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# Unsigned 16-bit immediate operands
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: ori 1, 2, -1
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ori 1, 2, -1
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: ori 1, 2, 65536
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ori 1, 2, 65536
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# Signed 16-bit immediate operands (extended range for addis)
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# CHECK: error: invalid operand for instruction
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addis 1, 0, -65537
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# CHECK: error: invalid operand for instruction
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addis 1, 0, 65536
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# D-Form memory operands
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# CHECK: error: invalid register number
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# CHECK-NEXT: lwz 1, 0(32)
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lwz 1, 0(32)
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# CHECK: error: invalid register name
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# CHECK-NEXT: lwz 1, 0(%r32)
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lwz 1, 0(%r32)
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: lwz 1, -32769(2)
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lwz 1, -32769(2)
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: lwz 1, 32768(2)
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lwz 1, 32768(2)
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# CHECK: error: invalid register number
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# CHECK-NEXT: ld 1, 0(32)
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ld 1, 0(32)
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# CHECK: error: invalid register name
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# CHECK-NEXT: ld 1, 0(%r32)
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ld 1, 0(%r32)
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: ld 1, 1(2)
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ld 1, 1(2)
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: ld 1, 2(2)
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ld 1, 2(2)
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: ld 1, 3(2)
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ld 1, 3(2)
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: ld 1, -32772(2)
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ld 1, -32772(2)
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# CHECK: error: invalid operand for instruction
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# CHECK-NEXT: ld 1, 32768(2)
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ld 1, 32768(2)
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