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https://github.com/c64scene-ar/llvm-6502.git
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a1535e3b9b
We were not considering the stated alignment on vector loads/stores, leading us to generate vector instructions even when we do not have sufficient alignment. Now, for IR like: %1 = load <4 x float>, <4 x float>* %ptr, align 4 we will generate correct, conservative PTX like: ld.f32 ... [%ptr] ld.f32 ... [%ptr+4] ld.f32 ... [%ptr+8] ld.f32 ... [%ptr+12] Or if we have an alignment of 8 (for example), we can generate code like: ld.v2.f32 ... [%ptr] ld.v2.f32 ... [%ptr+8] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213186 91177308-0d34-0410-b5e6-96231b3b80d8
78 lines
1.7 KiB
LLVM
78 lines
1.7 KiB
LLVM
; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
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target triple = "nvptx64-nvidia-cuda"
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; CHECK-LABEL: t1
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define <4 x float> @t1(i8* %p1) {
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; CHECK-NOT: ld.v4
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; CHECK-NOT: ld.v2
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; CHECK-NOT: ld.f32
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; CHECK: ld.u8
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%cast = bitcast i8* %p1 to <4 x float>*
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%r = load <4 x float>* %cast, align 1
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ret <4 x float> %r
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}
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; CHECK-LABEL: t2
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define <4 x float> @t2(i8* %p1) {
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; CHECK-NOT: ld.v4
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; CHECK-NOT: ld.v2
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; CHECK: ld.f32
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%cast = bitcast i8* %p1 to <4 x float>*
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%r = load <4 x float>* %cast, align 4
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ret <4 x float> %r
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}
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; CHECK-LABEL: t3
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define <4 x float> @t3(i8* %p1) {
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; CHECK-NOT: ld.v4
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; CHECK: ld.v2
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%cast = bitcast i8* %p1 to <4 x float>*
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%r = load <4 x float>* %cast, align 8
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ret <4 x float> %r
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}
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; CHECK-LABEL: t4
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define <4 x float> @t4(i8* %p1) {
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; CHECK: ld.v4
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%cast = bitcast i8* %p1 to <4 x float>*
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%r = load <4 x float>* %cast, align 16
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ret <4 x float> %r
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}
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; CHECK-LABEL: s1
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define void @s1(<4 x float>* %p1, <4 x float> %v) {
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; CHECK-NOT: st.v4
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; CHECK-NOT: st.v2
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; CHECK-NOT: st.f32
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; CHECK: st.u8
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store <4 x float> %v, <4 x float>* %p1, align 1
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ret void
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}
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; CHECK-LABEL: s2
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define void @s2(<4 x float>* %p1, <4 x float> %v) {
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; CHECK-NOT: st.v4
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; CHECK-NOT: st.v2
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; CHECK: st.f32
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store <4 x float> %v, <4 x float>* %p1, align 4
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ret void
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}
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; CHECK-LABEL: s3
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define void @s3(<4 x float>* %p1, <4 x float> %v) {
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; CHECK-NOT: st.v4
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store <4 x float> %v, <4 x float>* %p1, align 8
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ret void
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}
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; CHECK-LABEL: s4
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define void @s4(<4 x float>* %p1, <4 x float> %v) {
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; CHECK: st.v4
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store <4 x float> %v, <4 x float>* %p1, align 16
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ret void
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}
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