Tilmann Scheller 9e6f09d7ce ARM] Add Thumb-2 code size optimization regression test for BIC. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216880 91177308-0d34-0410-b5e6-96231b3b80d8		2014-09-01 12:53:29 +00:00
..
AArch64	[MachineSink] Use the real post dominator tree	2014-09-01 03:47:25 +00:00
ARM	ARM] Add Thumb-2 code size optimization regression test for BIC.	2014-09-01 12:53:29 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips] Don't use odd-numbered float registers for double arguments for fastcc	2014-08-22 09:23:22 +00:00
MSP430	Do not assume the value passed to memset is an i32.	2014-08-29 08:23:53 +00:00
NVPTX	[MachineSink] Use the real post dominator tree	2014-09-01 03:47:25 +00:00
PowerPC	[PowerPC] Add support for dcbtst and icbt (prefetch)	2014-08-23 23:21:04 +00:00
R600	R600/SI: Use mad for fsub + fmul	2014-08-29 16:01:14 +00:00
SPARC
SystemZ
Thumb	ARM / x86_64 varargs: Don't save regparms in prologue without va_start	2014-08-22 21:59:26 +00:00
Thumb2	ARM / x86_64 varargs: Don't save regparms in prologue without va_start	2014-08-22 21:59:26 +00:00
X86	[MachineSink] Use the real post dominator tree	2014-09-01 03:47:25 +00:00
XCore